HARDWARE REFERENCE A
3-8
3.6 INTERRUPTS
The Cyclone EP has seven interrupt sources. The CPU module assumes the interrupts are direct
mapped. Table 3-7 lists the interrupt sources and the corresponding XINT
signals. All interrupts are
level sensitive except the Squall II Module IRQ0 and IRQ1; these are dependent on the particular Squall
II Module installed.
The Sx and Kx processors have only four dedicated interrupt signals. A dip switch is provided on the Sx
and Kx CPU modules to map the six possible interrupt sources to the four direct mapped interrupt
inputs. Table 3-8 outlines the interrupt mapping for the Sx and Kx CPU modules.
The interrupt sources to INT1 and INT2 are selected using SW-1 on Sx and Kx modules. Table 3-9
shows all valid combinations. Positions 1 and 2 select the interrupt source to INT1 and both cannot be
ON or OFF simultaneously. Likewise, positions 3 and 4 select the interrupt source to INT2 and both
cannot be ON or OFF simultaneously.
Table 3-7. Interrupt Sources
XINT Signal Interrupt Source
XINT0
PLX PCI 9060
XINT1
Parallel Port
XINT2
PCI 9060 LSERR
XINT3 Deadlock Error
XINT4
Squall II Module IRQ0
XINT5
Squall II Module IRQ1
XINT6
Counter/Timers (Z8536)
XINT7
Serial Port (16C550)
Table 3-8. 80960Sx and Kx Interrupt Sources
INT Signal Interrupt Source
INT0 Counter/Timers (Z8536)
INT1 Serial Port UART (16C550) or Squall II Module IRQ1
INT2 Parallel Port or PLX PCI 9060
INT3 Squall II Module IRQ0
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