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Intel i960 Series User Manual

Intel i960 Series
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HARDWARE REFERENCE A
3-20
Table 3-21. Memory Region 0 Settings
Bits Function Setting
1:0 Bus Width 11 (32 Bit Bus Width)
5:2 Internal Wait States 0 (No Wait States)
6 READY Input Enable 1 (Enabled)
7 BTERM Input Enable 0 (Disabled)
Table 3-22. Local Address Space 0 Range Register
Field Description Read Write
Value after Reset
(Cold PC Reset)
0
Memory space indicator:
0 indicates Local address space 0 maps into PCI memory space.
1 indicates address space 0 maps into PCI I/O space.
Yes Yes 0
2:1
If mapped into memory space, encoding is as follows:
2 1 Meaning
0 0 locate anywhere in 32 bit PCI address space
0 1 locate below 1 Mbyte in PCI address space
1 0 locate anywhere in 64 bit PCI address space
1 1 reserved
If mapped into I/O space, bit 1 must be a 0. Bit 2 is included with bits 3 through
31 to indicate decoding range.
Yes Yes 0
3
If mapped into memory space, 1 indicates that reads are prefetchable. If
mapped into I/O space, bit is included with bits 2 through 31 to indicate
decoding range. 0 indicates reads are not prefetchable. This must be 0 on the
PCI-SDK Platform.
Yes Yes 0
31:4
Specifies which PCI address bits are used to decode a PCI access to local bus
space 0. Each bit corresponds to an address bit. Bit 31 corresponds to Address
bit 31. Set (=1) all bits to be included in decode; clear (=0) all other bits.
(Used in conjunction with PCI Configuration register 18H). Default is 1 Meg.
Yes Yes FFF0 000H
Table 3-23. Local Address Space 0 Local Base Address (Re-map) Register Description
Field Description Read Write
Value after Reset
(Cold PC Reset)
0
Space 0 Enable: 0 disables Decode of PCI addresses for Direct Slave
access to local space 0; 1 enables Decode.
Yes Yes 0
1 Not Used Yes Yes 0
3:2
If local space 0 is mapped into memory space, bits are not used. If mapped
into I/O space, bit is included with bits 4 through 31 for re-mapping.
Yes Yes 0
31:4
Re-map of PCI Address to Local Address Space 0 into a Local Address
Space. The bits in this register will re-map (replace) the PCI Address bits
used in decode as the Local Address bits.
Yes Yes 0

Table of Contents

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Intel i960 Series Specifications

General IconGeneral
BrandIntel
Modeli960 Series
CategoryComputer Hardware
LanguageEnglish

Summary

CHAPTER 1 INTRODUCTION

1.3 TECHNICAL SUPPORT, SCHEMATICS AND PLD EQUATIONS

Provides contact info for support and resource download.

CHAPTER 2 GETTING STARTED

2.1 PRE-INSTALLATION CONSIDERATIONS

Details components and prerequisites for developing programs on the Cyclone EP.

2.2 SOFTWARE INSTALLATION

Guides users through installing necessary development tools and software.

2.3 HARDWARE INSTALLATION

Provides step-by-step instructions for setting up the Cyclone EP hardware.

2.4 CREATING AND DOWNLOADING THE EXAMPLE PROGRAM

Explains how to compile, link, and load an example program.

CHAPTER 3 HARDWARE REFERENCE

3.3 CPU MEMORY MAP

Illustrates the organization of memory addresses for the i960 processors.

3.6 INTERRUPTS

Details the interrupt sources and their mapping on the Cyclone EP.

3.12 PLX PCI 9060 INTERFACE (PCI-SDK Platform Only)

Explains the PCI bus interface and the PLX 9060 chip.

CHAPTER 4 THEORY OF OPERATION

4.4 I/O INTERFACE

Details the design and implementation of the I/O subsystem and peripherals.

4.5 DRAM SUBSYSTEM

Explains the DRAM controller, memory access, and performance characteristics.

CHAPTER 5 SQUALL II MODULE INTERFACE

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