HARDWARE REFERENCE A
3-26
MON960 configures a 1 Gbyte region of PCI memory at PCI address 00000000H through 3FFFFFFFH
into local memory space at address 40000000H through 7FFFFFFFH. The register settings are:
Local Range for Direct Master-to-PCI Register (9CH) - C0000000H
• Since 30 bits are needed to encode a 1 Gbyte address space, the lower 30 bits of this register
are cleared (=0); the remaining upper 2 bits are set (=1). The set bits are replaced by the
contents of the upper two bits of the PCI Base Address Register (A8H) when a local-to-PCI
memory access is detected.
Local Bus Base Address for Direct Master-to-PCI Register (A0H) - 40000000H
• Since the upper two bits of the Local Range Register (9CH) are set, the upper two bits of this
register are used to detect a local access-to-PCI memory space. Effectively, this register remaps
the PCI address into local address space.
PCI Base Address for Direct Master-to-PCI Register (A8H) - 00000005H
• Bits 16 through 31 of this register are the PCI address to remap into local address space; the
lowest 8 bits are control settings. Bit 0 is set to enable the direct master memory access. Bit 1
controls direct master I/O access enable, and is cleared in this example. If the PCI-SDK
Platform were performing I/O accesses as well, this bit must be set. Bit 2 is the LOCK input
enable, and should be set. Bit 4 controls the master PCI read mode, and can be cleared. Bits 5
to 7 must be cleared on the PCI-SDK Platform.
Table 3-30. Local Bus Base Address Register for Direct Master-to-PCI Memory
Field Description Read Write
Value after Reset
(Cold PC Reset)
15:0 Not Used. Yes No 0
31:16 Assigns a value to the bits used to decode a Local-to-PCI memory access. Yes Yes 0
Table 3-31. Local Base Address for Direct Master-to-PCI IO/CFG Register
Field Description Read Write
Value after Reset
(Cold PC Reset)
15:0 Not Used Yes No 0
31:16
Assigns a value to the bits used to decode a Local-to-PCI I/O or configu-
ration access
Yes Yes 0
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