THEORY OF OPERATION A
4-8
4.5.2 DRAM Controller Implementation
The DRAM controller — the most complex section of the DRAM design — is implemented by an Intel
iFX780 Flex Logic device. The waveforms are controlled by the state machines implemented in the
PLDs. This section presents the waveforms and defines these state machines.
The DRAM controller runs one of four paths through the state machine depending on the processor. The
primary state machine runs in four different paths depending on the profile determined from processor
frequency and memory speed. A secondary state machine, which determines the bank select during
burst cycles, runs in two different paths determined by whether the host processor is a 32 or 16 bit
processor. Table 4-1 shows the profiles;
Figure shows the state diagrams for the DRAM controller.
Table 4-1. DRAM Profiles
Profile Frequency Frequency Memory Speed (PD3) Read Cycle Write Cycle
PF0 16 MHz 010 60 or 70ns X 3,1,1,1 3,2,2,2
PF0 20 MHz 011 60 or 70ns X 3,1,1,1 3,2,2,2
PF0 25 MHz 100 60ns 1 3,1,1,1 3,2,2,2
PF1 25 MHz 100 70ns 0 4,1,1,1,1 4,2,2,2,1
PF1 33 MHz 101 60 or 70ns X 4,1,1,1,1 4,2,2,2,1
PF1 40 MHz 110 60ns 1 4,1,1,1,1 4,2,2,2,1
PF2 40 MHz 110 70ns 0 5,2,2,2,1 4,2,2,2,1
PF2 50 MHz 111 60ns 1 5,2,2,2,1 4,2,2,2,1
PF3 50 MHz 111 70ns 0 5,2,2,2,2 4,2,2,2,2
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