A HARDWARE REFERENCE
3-19
3.12.1.3 RAM Region Configuration
The range for PCI-to-Local Address Space 0 Register (80H) (see Table 3-22) determines which address
bits are used to decode an access to a particular region.
User code should clear (write a “0” to) as many low bits in the Range Register as needed to address the
memory region, and all remaining higher bits should be set (write a “1”).
The Local Base Address for PCI-to-Local Address Space 0 Register (84H) (see Table 3-23) should then
be programmed with the local address of the RAM region. When a PCI access to the local memory
region is performed, the PCI address is changed to the local address by the PCI 9060 chip. The number
of set bits in the Range Register for that region determine the number of bits to be changed. This
effectively determines the size of the region. Memory space enable, pre-fetch, and PCI space are
controlled by the contents of the lower bits of the Range and Local Address Registers.
The Local Bus Region Descriptor for PCI-to-Local Accesses Register (98H) (see Table 3-25) contains
control settings for ROM region programming. Table 3-21 shows the required settings for memory
region 0 on the PCI-SDK Platform.
See Section 3.12.1.5, Memory Region Configuration Examples (pg. 3-22) for an illustration of RAM
region configuration on the PCI-SDK Platform.
Table 3-20. PCI Configuration Registers
Local
(Offset from
chip select
address)
31 24 23 16 15 8 7 0
PCI CFG
Register
Address
00H Device ID Vendor ID 00H
04H Status Command 04H
08H Class Code Revision ID 08H
0CH BIST Header Type Latency Timer Cache Line Size 0CH
10H PCI Base Address for Memory Mapped Runtime Registers 10H
14H PCI Base Address for I/O Mapped Runtime Registers 14H
18H PCI Base Address for Local Address Space 0 18H
1CH 1CH
20H 20H
24H 24H
28H Reserved 28H
2CH Reserved 2CH
30H PCI Base Address to Local Expansion ROM 30H
34H Reserved 34H
38H Reserved 38H
3CH Max_lat Min_Gnt Interrupt Pin Interrupt Line 3CH
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