Intel i960 Series User Manual

A SQUALL II MODULE INTERFACE
5-5
5.5 Squall Module Signal Descriptions
Table 5-2. Pin Description Nomenclature
Symbol Description
I Input only pin
O Output only pin
I/O Pin may be either an input or output
- Pin must be connected as described
S Synchronous. Inputs are synchronous to PMCLK. Outputs must meet setup and hold times relative
to PMCLK.
A( ) Asynchronous. Outputs may be asynchronous to PMCLK.
A(E) Edge Sensitive Output
A(L) Level Sensitive Output
SL( ) While EHOLD
and EHLDA are inactive, the pin functions in the slave mode.
SL(O) Output
SL(I) Input
SL(I/O) As an input or an output
M( ) When EHOLD
and HLDA are asserted, the module is in master mode.
M(I) Input
M(O) Output
M(I/O) As an input or output
Table 5-3. Squall Module Signal Descriptions (Sheet 1 of 3)
Name Type Description
S_A[02:31]
SL(I)
M(O)
S
Address Bus carries the upper 30 bits of address. The byte enable signals indicate
the selected byte in each word.
S_D[00:31]
I/O
S
Data Bus carries 32, 16, or 8 bit data depending on the bus width configured in the
Memory Region Table. For a bus width of 8 bits, data lines D[00:07] are used. For
16 bits, D[00:15] are used. For 32 bits, the full bus is used. In master mode, all
transfers with the memory use full data bus.

Intel i960 Series Specifications

General

Brand	Intel
Model	i960 Series
Category	Computer Hardware
Language	English

Summary

CHAPTER 1 INTRODUCTION

1.3 TECHNICAL SUPPORT, SCHEMATICS AND PLD EQUATIONS

Provides contact info for support and resource download.

CHAPTER 2 GETTING STARTED

2.1 PRE-INSTALLATION CONSIDERATIONS

Details components and prerequisites for developing programs on the Cyclone EP.

2.2 SOFTWARE INSTALLATION

Guides users through installing necessary development tools and software.

2.3 HARDWARE INSTALLATION

Provides step-by-step instructions for setting up the Cyclone EP hardware.

2.4 CREATING AND DOWNLOADING THE EXAMPLE PROGRAM

Explains how to compile, link, and load an example program.

CHAPTER 3 HARDWARE REFERENCE

3.1 CONNECTORS, SWITCHES AND LEDS

3.2 CPU MODULES

3.3 CPU MEMORY MAP

Illustrates the organization of memory addresses for the i960 processors.

3.4 INTERLEAVED DRAM

3.5 FLASH MEMORY

3.6 INTERRUPTS

Details the interrupt sources and their mapping on the Cyclone EP.

3.7 CONSOLE SERIAL PORT

3.8 PARALLEL PORT

3.11 SQUALL II MODULE INTERFACE

3.12 PLX PCI 9060 INTERFACE (PCI-SDK Platform Only)

Explains the PCI bus interface and the PLX 9060 chip.

CHAPTER 4 THEORY OF OPERATION

4.2 CLOCK GENERATION

4.3 POWER MONITOR AND RESET

4.4 I/O INTERFACE

Details the design and implementation of the I/O subsystem and peripherals.

4.5 DRAM SUBSYSTEM

Explains the DRAM controller, memory access, and performance characteristics.

CHAPTER 5 SQUALL II MODULE INTERFACE

5.4 SQUALL II MODULE SIGNAL DEFINITIONS

5.5 SQUALL MODULE SIGNAL DESCRIPTIONS

5.6 SQUALL II MODULE TIMING