Intel i960 Series User Manual

THEORY OF OPERATION A
4-6
4.4.3.2 Serial Port
The Cyclone EP provides one RS-232 serial port which is used for communications and program
download. This port implements the signals for transmit, receive, clear-to-send and request. Chapter 2,
GETTING STARTED contains extensive information on communications and downloading.
The serial port interface provides asynchronous RS-232 standard communication for monitors or user-
defined applications. The serial port interface consists of two components:
• 16550CV Universal Asynchronous Receiver/Transmitter (UART) with FIFOs
• MAX232 +5V Powered RS-232 Driver/Receiver
National Semiconductor's* 16550 UART implements an independent asynchronous serial port on the
Cyclone EP. The serial port implements a transmit (TXD) and a receive (RXD) line. The serial port also
provides a clear-to-send (CTS) and request-to-send (RTS) signal to interface to modem applications.
A 1.843 MHz oscillator provides the baud rate clock for the serial port. With this oscillator, the 16550 is
able to provide serial transmit and receive at up to 115.2 KBaud. For more information on programming
the 16550, refer to Data Communications Local Area Networks UARTs Handbook, National Semicon-
ductor Corporation.
TXD and RTS from the 16550 are translated to RS-232 compatible signals with a MAX232 buffer/
receiver chip. RXD and CTS are converted into TTL levels by the MAX232 and routed as inputs to the
UART chip. The MAX232 contains an internal charge pump that generates the RS-232 voltage levels.
4.5 DRAM SUBSYSTEM
Cyclone EP features DRAM and a DRAM controller which operates with all members of the i960
processor family. The DRAM controller runs with minimum wait states at 16, 20, 25, 33, and 40 MHz
processor clock frequencies. The design uses interleaved banks of fast page mode DRAM to reduce the
wait states during burst accesses. DRAM may be expanded from 2 Mbytes to 8 or 32 Mbytes of
memory. Refer to Section 3.4, INTERLEAVED DRAM (pg. 3-5) for related information.
4.5.1 Page Mode DRAM SIMM Review
Page mode DRAM allows faster memory access by keeping the same row address while selecting
random column addresses within that row. A new column address is selected by deasserting CAS
while
keeping RAS
active and then asserting CAS with the new column address valid to the DRAM. Page
mode operation works very well with burst buses in which a single address cycle can be followed by up
to four data cycles.
Also, all WE
pins on the SIMM are tied to a common WE line; this line requires the Cyclone EP design
to employ early write cycles. In an early write cycle, the write data is referenced to the falling edge of
CAS
, not the falling edge of WE.
Each SIMM also has four CAS
lines, one for each eight (nine) bits in a 32-bit (36-bit) SIMM module.
The four CAS
lines controls writing individual bytes within the SIMM.

Intel i960 Series Specifications

General

Brand	Intel
Model	i960 Series
Category	Computer Hardware
Language	English