A THEORY OF OPERATION
4-3
4.4.1 Functional Blocks
The I/O design comprises four distinct blocks: data path, control logic, registered I/O, and I/O
peripheral devices. The schematic for the design is hierarchical.
4.4.2 I/O Control Timing
The chip selects and I/O data buffer control are synchronous set-and-hold flip flops in the iFX780
device. The flip flops are set to active upon ADS
and the proper address, and are held active until
BLAST
and READY are asserted.
NOTE:
The 80960Kx does not generate BLAST. For the Cyclone EP, BLAST is generated by a PAL
on the CPU module.
The chip select signals cause the I/O control state machine to operate. The state machine generates the
proper timing for the read and write strobes, READY
, and the recovery time which many of the I/O
devices require.
All timing assumes a 50 MHz processor clock to ensure that all minimum timing requirements are met
over the entire range of processor clocks (16 to 50 MHz). The state diagram for the I/O control state
machine is shown in Figure 4-1.
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