Intel i960 Series User Manual

A THEORY OF OPERATION
4-3
4.4.1 Functional Blocks
The I/O design comprises four distinct blocks: data path, control logic, registered I/O, and I/O
peripheral devices. The schematic for the design is hierarchical.
4.4.2 I/O Control Timing
The chip selects and I/O data buffer control are synchronous set-and-hold flip flops in the iFX780
device. The flip flops are set to active upon ADS
and the proper address, and are held active until
BLAST
and READY are asserted.
NOTE:
The 80960Kx does not generate BLAST. For the Cyclone EP, BLAST is generated by a PAL
on the CPU module.
The chip select signals cause the I/O control state machine to operate. The state machine generates the
proper timing for the read and write strobes, READY
, and the recovery time which many of the I/O
devices require.
All timing assumes a 50 MHz processor clock to ensure that all minimum timing requirements are met
over the entire range of processor clocks (16 to 50 MHz). The state diagram for the I/O control state
machine is shown in Figure 4-1.

Intel i960 Series Specifications

General

Brand	Intel
Model	i960 Series
Category	Computer Hardware
Language	English

Summary

CHAPTER 1 INTRODUCTION

1.3 TECHNICAL SUPPORT, SCHEMATICS AND PLD EQUATIONS

Provides contact info for support and resource download.

CHAPTER 2 GETTING STARTED

2.1 PRE-INSTALLATION CONSIDERATIONS

Details components and prerequisites for developing programs on the Cyclone EP.

2.2 SOFTWARE INSTALLATION

Guides users through installing necessary development tools and software.

2.3 HARDWARE INSTALLATION

Provides step-by-step instructions for setting up the Cyclone EP hardware.

2.4 CREATING AND DOWNLOADING THE EXAMPLE PROGRAM

Explains how to compile, link, and load an example program.

CHAPTER 3 HARDWARE REFERENCE

3.1 CONNECTORS, SWITCHES AND LEDS

3.2 CPU MODULES

3.3 CPU MEMORY MAP

Illustrates the organization of memory addresses for the i960 processors.

3.4 INTERLEAVED DRAM

3.5 FLASH MEMORY

3.6 INTERRUPTS

Details the interrupt sources and their mapping on the Cyclone EP.

3.7 CONSOLE SERIAL PORT

3.8 PARALLEL PORT

3.11 SQUALL II MODULE INTERFACE

3.12 PLX PCI 9060 INTERFACE (PCI-SDK Platform Only)

Explains the PCI bus interface and the PLX 9060 chip.

CHAPTER 4 THEORY OF OPERATION

4.2 CLOCK GENERATION

4.3 POWER MONITOR AND RESET

4.4 I/O INTERFACE

Details the design and implementation of the I/O subsystem and peripherals.

4.5 DRAM SUBSYSTEM

Explains the DRAM controller, memory access, and performance characteristics.

CHAPTER 5 SQUALL II MODULE INTERFACE

5.4 SQUALL II MODULE SIGNAL DEFINITIONS

5.5 SQUALL MODULE SIGNAL DESCRIPTIONS

5.6 SQUALL II MODULE TIMING