THEORY OF OPERATION A
4-10
4.6 CAS Generation
The CAS
signals to the A and B banks of DRAM are generated from a high speed 20V8 PAL with clock
to output timing of 5 ns. The BANKSEL signal from the iFX780 determines which set of CAS
signals
is asserted. The processor’s BEx
signals are used to qualify the CAS signals.
4.7 Refresh Generation
CAS
before RAS refresh is performed. A counter is buried in the iFX780 counting 16 µs from the
4 MHz clock. Every 16 µs the signal REFPEND is asserted. If state S0 is entered, and REFPEND is
active, the state machine branches to perform refresh. REF
is asserted, indicating to the CAS generation
PAL to assert the CAS
signals. The RAS is then asserted and the proper number of cycles are waited.
REF, RAS
, and the CAS are negated and REFPEND is also negated. The state machine returns to S0
ready to run processor memory cycles.
To Next Page
Loading...
Need help?
General
