HARDWARE REFERENCE A
3-28
On the Jx processor, an interrupt (XINT3) is asserted. The Kx and Sx processors, however, have no free
interrupt lines. As a result, there is no way for these processors to detect the error. The XINT3
interrupt
on the Jx processor is intended only to inform the system designer that a deadlock error has occurred,
and is a non-recoverable error. On the Sx, Kx, and Jx processors, the system designer must ensure that
only memory is shared either on the host or PCI-SDK Platform, but never both.
The Cx and Hx processors handle the deadlock condition transparently, once the PCI 9060 is configured
to signal a deadlock. On the Jx, user code must detect the fatal error interrupt on XINT3
. The interrupt
should be connected to a handler which provides a signal to the designer that a fatal error has occurred.
The Local Expansion ROM Local Base Address/BREQo Control Register (94H) on the PCI 9060 must
be configured at initialization to handle the deadlock condition. To avoid deadlock, the PCI 9060 must
be programmed to detect a timeout and assert BREQo, which either causes the local processor to
backoff or — in the case of the Jx — causes the processor to be interrupted after the access is complete,
indicating an error. The lower four bits of the Local Expansion ROM Address/BREQo Control Register
(94H) should be set to the number of local bus clocks before a timeout is detected, and the Local Bus
BREQo Enable bit should be set to 1.
3.12.4 Signalling Init Done
Initialization code must set the Local Init Status bit in the EEPROM Control/Init Control Register
(ECH) before finishing. Until this bit is set, the PCI 9060 responds to any attempted master accesses
from PCI by signalling RETRY. Once this bit is set, BIOS code on the host system can proceed with the
remainder of the initialization.
3.12.5 PCI Interrupts
The PCI 9060 can be configured to generate PCI interrupts to the host system in response to a number of
events. Doorbell interrupts, which are described in Section 3.12.6, Mailbox Registers and Doorbell
Interrupts (pg. 3-31), provide a simple mechanism for software to send/receive signals to/from the host
processor.
The PCI 9060 can also be configured to interrupt the host processor if any PCI error conditions, such as
LSERR
or a master or target abort, are detected. In some applications it may be useful to configure the
PCI 9060 to generate a PCI interrupt whenever it generates a local interrupt. This allows the host system
or another PCI master to receive automatic notification whenever a local interrupt is triggered by the
PCI 9060, and take some appropriate action.
All interrupt enabling and detection on the PCI 9060 is handled through the Interrupt Control and Status
Register (E8H) (Table 3-33). If any PCI or local interrupts are used, the PCI or Local Interrupt Enable
bit in this register must be set — in addition to the separate enable bits for the interrupt sources in use.
Interrupt handling code on the i960 processor should check the interrupt active bits in the Interrupt
Control and Status Register (E8H) to determine the source of the interrupt, and call an appropriate
interrupt service routine to process the interrupt.
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