SQUALL II MODULE INTERFACE A
5-18
5.8 Squall II Module Signal Loading and Logic Selection
Selection of logic families for Squall II Modules deals mostly with the edge rate of the outputs. CMOS
logic families, although they use less power than their bipolar predecessors, can be very noisy due to
very fast edges transitioning full 5 volt swings from rail to rail. The high-speed 5 volt transitions can
result in large under and over shoots, ringing, and ground bounce. Logic families such as ACT, FCT,
and ACL all exhibit such tendencies.
Newer BiCMOS Logic families such as BCT or ABT are recommended. These families, like older TTL
logic, switch between 3.5 v and ground, and contain edge control circuitry. The same consideration is
true for programmable logic. Some manufacturers boast of higher speed parts, but achieve that objective
by increasing the signal edge transitions. Designers should evaluate the transitions before deciding to
use a part in a Squall II Module design.
The loading of the Squall II Module interface signals is very important. The majority of the signals are
bussed between the Squall II Module connector, the shared memory, the processor interface, and the
PCI bus interface. For best results, restrict these signals to two loads on each Squall II Module. Some
signals are routed to an individual Squall II Module and, therefore, may be more heavily loaded. Refer
to Table 5-7 for specific loading restrictions.
5.9 Squall II Module Clock Termination
Individual clock signals are driven to each Squall II Module. Clock signals should be terminated with an
AC termination of 470 pF and 51 ohms to ground as shown in Figure 5-10. Care should be taken to
locate the loads close to the end of the signal, especially in double sized modules.
Figure 5-10. Squall II Module Clock Termination
Table 5-7. Squall II Module Signal Loading
Signal Loads
S_A, S_D, S_BE, S_W/R, S_ADS, S_READY, S_BLAST, S_EXTEND, S_LOCK 2
SQSEL 6
RESET 10
SQBG 6
PMCLK 5
PMCLK
470 pF
51 Ohms
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