Intel i960 Series User Manual

A HARDWARE REFERENCE
3-25
Local-to-PCI bus options are controlled by settings in the PCI Base Address Register (A8H). Bit 0 must
be set (=1) to enable accesses-to-PCI memory space; bit 1 must be set to enable I/O accesses. Bit 2
controls LOCK input from the PCI bus, and should be set. Bit 3 controls pre-fetch size for PCI master
accesses, and should be cleared (=0). Bit 4 is used to change the behavior of the PCI 9060 when the read
FIFO is full. It can remain cleared unless there is some reason to change it. Bits 5 to 7 control the
programmable almost full flag on the PCI 9060. This feature is not implemented on the PCI-SDK
Platform, so these bits should all be cleared.
Table 3-28. Local Range Register for Direct Master-to-PCI Description
Field Description Read Write
Value after Reset
(Cold PC Reset)
15:0 Not Used (64 Kbyte increments) Yes No 0
31:16
Specifies which Local address bits are used to decode a Local-to-PCI bus
access. Each bit corresponds to an address bit. Bit 31 corresponds to
Address bit 31. Set (=1) all bits included in decode; clear (=0) all other bits.
Yes Yes 0
Table 3-29. PCI Base Address (Re-map) Register for Direct Master-to-PCI Description
Field Description Read Write
Value after
Reset (Cold
PC Reset)
0
Direct Master Memory Access Enable:
0 disables decode of Direct Master Memory accesses.
1 enables decode of Direct Master Memory accesses.
Yes Yes 0
1
Direct Master I/O Access Enable:
0 disables decode of Direct Master I/O accesses.
1 enables decode of Direct Master I/O accesses.
Yes Yes 0
2
LOCK Input Enable:
0 disables the LOCK input.
1 enables LOCK input (enables PCI locked sequences).
Yes Yes 0
3
Direct Master Read Pre-fetch Size control:
0 - the PCI 9060 continues to prefetch read data until the Direct Master access is
finished. This may result in an additional four un-needed Lwords being pre-fetched from
the PCI bus.
1 - PCI 9060 reads up to four Lwords from the PCI bus for each Direct Master burst
read access. Do not use this mode for direct master burst reads that exceed four
Lwords.
Yes Yes 0
4
Direct Master PCI read mode:
0 - PCI 9060 releases the PCI bus when the read FIFO becomes full.
1 - PCI 9060 keeps the PCI bus and deasserts IRDY when the read FIFO becomes full.
Yes Yes 0
7:5
Programmable Almost Full Flag. When the number of entries in the 8-deep direct
master write FIFO exceed this value, the output pin DMPAF# is asserted low. Not Used.
Yes Yes 0
15:8 Not Used. Yes No 0
31:16
Re-map of Local-to-PCI space into a PCI address space. These bits re-map (replace)
Local address bits used in decode as the PCI address bits.
Yes Yes 0

Intel i960 Series Specifications

General

Brand	Intel
Model	i960 Series
Category	Computer Hardware
Language	English