SQUALL II MODULE INTERFACE A
5-4
As with on-board EEPROM, bytes are read from and written to the 24C08 EEPROM most significant
bit (bit 7) first and least significant bit (bit 0) last.
Figure 5-3. Squall II Module EEPROM Memory Map
5.4 Squall II Module Signal Definitions
Squall II Module devices can be accessed by the processor and may access the shared memory via a
100-pin connector. This section describes the signals provided on the Squall II Module interface
connector. The signals are an enhanced set of the i960 external bus signals. Familiarity with the
operation of the i960 external bus helps the user to understand the Squall II Module Interface. Refer to
the i960 microprocessor user’s manual for detailed explanations.
The signals are described relative to the circuitry on the Squall II Module (an input to the CPU or
memory would be an output from the Squall II Module). Master and slave designations are used to
describe different operating modes of the Squall Interface.
• The Squall II Module is a slave when it is being accessed by the processor (SQBG
inactive).
• The Squall II Module is a master when its circuitry has been granted mastership of the shared
memory bus (SQBG
asserted by arbitration circuitry in response to a SQBR).
All output and I/O pins have been provided with the proper pull up resistors on the host board and may
be left unconnected if desired. Table 5-2 presents the legend for interpreting the pin descriptions.
Module-specific data
Module revision level
Module version
Reserved
Interrupt Detection Mode
Region Configuration Word
(see the particular module’s user manual)
000H
003H
004H
005H
007H
008H
009H
00AH
7FFH
ADDRESS DESCRIPTION
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