HARDWARE REFERENCE A
3-10
3.8 PARALLEL PORT
A Centronics PC-compatible receive-only parallel port is implemented on the Cyclone EP. You access
and control the parallel port by using three memory-mapped registers (see Table 3-11):
• Parallel port data register
• Parallel port status register
• Parallel port control register
The port uses a DB25 connector with PC-compatible pin assignments. A cable is included with the
Cyclone EP to facilitate downloading of code from a host development workstation or PC.
3.8.1 Parallel Port Bit Assignments
Table 3-12 shows the read-only parallel port status register bit assignments.
The parallel port control register is a write-only 8-bit register that controls parallel port operation. This
register also contains an interrupt enable bit (PINTEN) that enables the parallel port interrupt. When the
interrupt is enabled, an interrupt is signaled when either PSTROBE
or PPINIT is asserted. The interrupt
is cleared when the parallel port data register is read. Table 3-12 shows the parallel port control register.
Table 3-11. Parallel Port Addresses
Address Read Register Write Register
B008 0000H Status Register Control Register
B008 0004H Data Register Unused
Table 3-12. Parallel Port Status Register Bit Assignments
Bit Signal Mnemonic Signal Name
7 not used —
6 not used —
5 BUSY Bus Busy
4 ACK Acknowledge
3 PPSLCTIN Select In
2 PPFEED Paper Feed
1 PSTROBE
Data Strobe
0 PPINIT
Port Initialize
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