HARDWARE REFERENCE A
3-18
3.12.1.2 PCI-to-Local Configuration
Before PCI 9060 memory can be accessed through the PCI interface, code on the PCI-SDK Platform
must configure the memory regions which will be visible to PCI masters. The PCI 9060 allows one
RAM region and one PCI expansion ROM area to be configured as PCI regions.
Both of these regions are controlled by the contents of registers in the Local Configuration group (see
Table 3-19) which determine region size, location in local memory space, and where it will be mapped
in PCI space. Table 3-20 shows the PCI configuration registers. The size and local address are set by
programming the Range and Local Base Address registers for the region; the location of the region in
PCI space is subsequently set in the PCI configuration header by the host system, depending on the
register control bit settings.
Table 3-19. Local Configuration Registers
Local
(Offset from
chip select address)
31 0
PCI
(Offset from Runtime
Base address)
80H Range for PCI-to-Local Address Space 0 00H
84H Local Base Address (re-map) for PCI-to-Local Address Space 0 04H
88H Reserved 08H
8CH Reserved 0CH
90H Range for PCI-to-Local Expansion ROM 10H
94H Local Base Address (re-map) for PCI-to-Local Expansion ROM and BREQo control 14H
98H Bus Region Descriptors for PCI-to-Local Accesses 18H
9CH Range for Direct Master-to-PCI 1CH
A0H Local Base Address for Direct Master-to-PCI Memory 20H
A4H Local Base Address for Direct Master-to-PCI IO/CFG 24H
A8H PCI Base Address (re-map) for Direct Master-to-PCI 28H
ACH PCI Configuration Address Register for Direct Master-to-PCI IO/CFG 2CH
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