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HARDWARE REFERENCE A

3-24

• A 512 Kbyte space is being mapped, so the lower 19 bits of this register are needed to decode

an access. The remaining 13 upper bits are set to 1, so these bits are replaced with the contents

of the Local Base Address for PCI-to-Local Expansion ROM (94H). The lower 10 bits of this

Local Base Address for PCI-to-Local Expansion ROM (94H) - E0000017H

• Bits 11 to 31 of this register contain the local address of the expansion ROM. Bits 5 to 10 are

unused. Bit 4 is the Local Bus BREQo Enable, and is discussed in Section 3.12.3, Deadlock

Configuration (pg. 3-27). This bit must be enabled for proper operation of the PCI-SDK

Platform. Bits 0 to 3 encode the number of delay clocks to wait before asserting BREQo. This

value is also discussed in the section on deadlock. Setting these bits to 7 selects a 56-clock

delay.

Local Bus Region Descriptor for PCI-to-Local Accesses Register (98H) -

• All ROM regions on the PCI-SDK Platform should use the settings in Table 3-26 for this

3.12.2 Local-to-PCI Configuration

To use the PCI-SDK Platform as a PCI bus master, the PCI 9060 requires that the portion of PCI space

to be accessed is mapped into the local processor's address space. The PCI 9060 can access memory or

I/O space on the PCI bus through region mapping, and it can also generate configuration cycles.

Address mapping is controlled by five registers in the Local Configuration group. If the PCI-SDK

Platform is used to access PCI space, the Range for Direct Master-to-PCI Register (9CH) (Table 3-28)

and PCI Base Address for Direct Master-to-PCI Register (A8H) (Table 3-29) registers must be

programmed for local-to-PCI accesses.

PCI memory space and I/O space are mapped to separate local processor regions. To access PCI

memory space, the Local Base Address for Direct Master-to-PCI Memory Register (A0H) (Table 3-30)

must be programmed with the local address to which PCI memory space should be mapped.

For PCI-SDK Platform access to PCI I/O or configuration spaces, the Local Base Address for Direct

Master-to-PCI IO/CFG Register (A4H) (Table 3-31) must also be programmed with a local base

address.

If both memory and I/O spaces are to be accessed, the local base address registers should be

programmed with different values to prevent address spaces from overlapping. Configuration cycles

produced by the PCI 9060 are controlled by the PCI Configuration Address Register (ACH) (Table 3-

32). If the Configuration Enable bit in this register is set, the PCI 9060 converts I/O space accesses to

configuration space accesses using the values programmed into this register.

Intel i960 Series User Manual

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