A HARDWARE REFERENCE
3-23
Local Address Space 0 Local Base Address Register (84H) - A0000001H
• The upper 9 bits of this register replace those used to access the local memory from PCI, since
9 bits are set in the Range Register. Bit 0 is set, enabling PCI accesses to this space. Bit 1 is not
used and, since this region is mapped into memory space, bits 2 and 3 are also unused.
Local Bus Region Descriptor for PCI-to-Local Accesses Register (98H) -
• All RAM regions on the PCI-SDK Platform should use the settings in Table 3-21 for this
register.
MON960 configures the PCI-SDK Platform's 512 Kbyte expansion ROM address range, E0000000H to
E007FFFFH, as PCI expansion ROM. To configure this memory as a PCI expansion ROM region, the
following settings must be made:
Range for PCI-to-Local Expansion ROM Register (90H) - FFF80000H
Table 3-26. Local Expansion ROM Local Base Address (Re-map) and BREQo Register Description
Field Description Read Write
Value after Reset
(Cold PC Reset)
3:0
Direct Slave BREQo Delay Clocks. Number of local bus clocks in which a
Direct Slave HOLD request is pending and a Local Direct Master access is
in progress and not being granted the bus (HOLDA) before asserting
BREQ0. Once asserted, BREQo remains asserted until the PCI 9060
receives HOLDA (LSB= 8 clocks). See Section 3.12.3, Deadlock Configu-
ration (pg. 3-27) for setting this register.
Yes Yes 0
4
Local Bus BREQo Enable. A 1 value enables the PCI 9060 to assert the
BREQo output.
Yes Yes 0
10:5 Not Used Yes No 0
31:11
Re-map of PCI Expansion ROM space into a Local address space. The bits
in this register re-map (replace) the PCI address bits used in decode as the
Local address bits.
Yes Yes FFFF0000H
Table 3-27. Local Expansion ROM Range Register Description
Field Description Read Write
Value after Reset
(Cold PC Reset)
10:0 Not used Yes Yes 0
31:11
Specifies which PCI address bits are used to decode a PCI-to-local
bus expansion ROM. Each bit corresponds to an Address bit 31. Set
(=1) all bits included in decode; clear (=0) all others (Used in
conjunction with PCI Configuration register 30H). Default is 64
KBytes.
Yes Yes FFFF0000H
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