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A HARDWARE REFERENCE

3-17

NOTE:

Configure the PCI 9060 for 32-bit i960 Cx CPU mode regardless of the actual CPU module

installed.

For configuration examples, refer to the MON960 configuration code for the PCI 9060 included with

the PCI-SDK Platform. The initial configuration can be divided into the following steps:

• PCI-to-local address mapping setup

• Local-to-PCI address mapping setup

• Deadlock handling setup

3.12.1.1 Accessing Configuration Registers

Code running on the PCI-SDK Platform can access configuration registers on the PCI 9060 by adding

the offset of the desired register to the PCI 9060 select address (8000 0000H). (Refer to PLX PCI 9060

documentation for offset values.) Thus, to access Mailbox Register 0 (C0H), the address would be

8000 00C0H.

The register descriptions in PLX PCI 9060 documentation indicate whether a register can be read and/or

written from the local bus. Writing to a read-only register or bit location on the PCI 9060 has no ill-

effects; the value is simply not latched.

Once the PCI-SDK Platform is initialized by local code, some of its configuration registers are

accessible to other PCI masters. The PCI Configuration, Local Configuration, and Shared Run Time

space on the host system, but the other two groups are accessed at offsets above the PCI 9060 register

base address. To access PCI configuration registers from the PCI bus, host-side code must use the

appropriate PCI BIOS services.

The base address for the Local Configuration and Shared Run Time registers may be in either memory,

I/O space, or both, depending on how the i960 processor configures the PCI 9060. During start-up, the

BIOS on the host system assigns base addresses to the PCI 9060. Host-side code can determine the base

address of the PCI 9060 registers by reading the PCI Base Address for Memory Mapped Runtime

Registers (10H) and the PCI Base Address for I/O Mapped Runtime Registers (14H) from the PCI

Configuration group using configuration cycles. A non-zero value in these registers indicates that PCI

9060 registers are mapped into the corresponding PCI space. It is possible for runtime registers to be

mapped into both memory and I/O space on the host system.

Table 3-19 shows the local configuration register offsets; Table 3-20 shows the PCI configuration

registers. If a register will be accessed by the host from the PCI bus, create the register address by

adding its PCI offset to the base address of either the Memory Mapped Runtime Registers or the I/O

Mapped Runtime Registers. The same PCI offsets should be used whether the registers are mapped in

memory or I/O space.

Until the PCI 9060 has been configured by code running on the PCI-SDK Platform, it will respond to

any PCI accesses by signalling RETRY.

Intel i960 Series User Manual

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