Intel i960 Series

A CONTENTS
v
CHAPTER 5
SQUALL II MODULE INTERFACE
5.1 Physical Attributes.......................................................................................................................................... 5-1
5.2 Power Requirements ...................................................................................................................................... 5-3
5.3 Squall II Module Serial EEPROM................................................................................................................... 5-3
5.4 Squall II Module Signal Definitions................................................................................................................. 5-4
5.5 Squall Module Signal Descriptions................................................................................................................. 5-5
5.6 Squall II Module Timing.................................................................................................................................. 5-8
5.6.1 Squall II Module Slave Timing .................................................................................................................. 5-8
5.6.2 Squall II Module Master Timing .............................................................................................................. 5-12
5.7 Squall II Module Connector .......................................................................................................................... 5-17
5.8 Squall II Module Signal Loading and Logic Selection................................................................................... 5-18
5.9 Squall II Module Clock Termination.............................................................................................................. 5-18
APPENDIX A
PARTS LIS T
FIGURES
Figure 1-1 Cyclone EP and PCI-SDK Platform Functional Block Diagram.......................................................... 1-1
Figure 2-1 Download Messages .......................................................................................................................... 2-5
Figure 2-2 Program Execution Messages............................................................................................................ 2-6
Figure 3-1 Cyclone EP and PCI-SDK Platform Physical Diagram....................................................................... 3-1
Figure 3-2 DRAM Memory Map for Cyclone EP.................................................................................................. 3-5
Figure 3-3 CIO Port A ........................................................................................................................................ 3-12
Figure 3-4 CIO Port B ........................................................................................................................................ 3-13
Figure 3-5 CIO Port C........................................................................................................................................ 3-14
Figure 3-6 Non-Chaining DMA Initialization....................................................................................................... 3-33
Figure 3-7 Chaining DMA Initialization............................................................................................................... 3-34
Figure 4-1 I/O Control State Machine .................................................................................................................. 4-4
Figure 4-2 Parallel Port Timing Signals ............................................................................................................... 4-5
Figure 4-3 Two-way Interleaving.......................................................................................................................... 4-7
Figure 4-4 DRAM State Machine......................................................................................................................... 4-9
Figure 5-1 Squall II Module Component Height Allowance ................................................................................. 5-1
Figure 5-2 Squall II Module Dimensions.............................................................................................................. 5-2
Figure 5-3 Squall II Module EEPROM Memory Map ........................................................................................... 5-4
Figure 5-4 Squall II Slave Read and Write Timing Diagram .............................................................................. 5-10
Figure 5-5 Squall II Slave Burst Read Timing Diagram ..................................................................................... 5-11
Figure 5-6 Squall II Slave Burst Write Timing Diagram...................................................................................... 5-12
Figure 5-7 Squall II Master Read and Write Timing Diagram ............................................................................ 5-14
Figure 5-8 Squall II Master Burst Read and Write Timing Diagram................................................................... 5-15
Figure 5-9 Squall II Master Read Using S_EXTEND
......................................................................................... 5-16
Figure 5-10 Squall II Module Clock Termination.................................................................................................. 5-18