EasyManua.ls Logo

Intel i960 Series

Intel i960 Series
102 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
SQUALL II MODULE INTERFACE A
5-10
Figure 5-4. Squall II Slave Read and Write Timing Diagram
1 2 3 4 5 6 7 8 9 10
D600A
PMCLK
S_ADS
SQxSEL
S_BLAST
S_ADDR
S_BEx
S_W/R
S_DATA
S_READY
NOTE: Diagram shows two wait states; any number of wait states are acceptable.
t1 t1 t1 t1
t2 t2 t2 t2
t6 t6 t6 t6
t7 t7 t7
t7 t7 t7
t8 t8
t4 t5
t11 t11
t9 t10
t9 t10

Table of Contents

Related product manuals