EasyManuals Logo
Home>Intel>Server Board>S1200V3RP

Intel S1200V3RP Technical Product Specification

Intel S1200V3RP
270 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #28 background imageLoading...
Page #28 background image
Functional Architecture Intel® Server Board S1200V3RP TPS
Revision 1.2
14
Intel
®
64 Architecture
Intel
®
Streaming SIMD Extensions 4.2 (Intel
®
SSE4.2)
Intel
®
Advanced Vector Extensions 2.0 (Intel
®
AVX2)
Advanced Encryption Standard New Instructions (AES-NI)
Intel
®
Hyper-Threading Technology
Execute Disable Bit
Intel
®
Turbo Boost Technology
PCLMULQDQ Instruction
Intel
®
Transactional Synchronization Extensions (Intel
®
TSX)
PAIR Power Aware Interrupt Routing
SMEP Supervisor Mode Execution Protection
3.3 Integrated Memory Controller (IMC) and Memory Subsystem
Integrated into the processor is a memory controller. Only ECC memory is supported on this
platform. Each processor provides two DDR3L Unbuffered Dual In-Line Memory Modules
(UDIMM) channels that support the following:
ECC Unbuffered DDR3L
Single-channel and dual-channel memory organization modes
Data burst length of eight cycles for all memory organization modes
Memory DDR3 data transfer rates of 1333, and 1600 MT/s
64-bit wide channels
DDR3L I/O Voltage of 1.35 V
Theoretical maximum memory bandwidth of:
- 21.3 GB/s in dual-channel mode assuming 1333 MT/s
- 25.6 GB/s in dual-channel mode assuming 1600 MT/s
1 Gb, 2 Gb, and 4 Gb DDR3L DRAM device technologies are supported
- Using 4 Gb DRAM device technologies, the largest system memory capacity
possible is 32 GB, assuming Dual Channel Mode with four x8 dual ranked DIMM
memory configuration
Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank devices)
Processor on-die Vref generation for DDR DQ Read and Write as well as CMD/ADD
Command launch modes of 1n/2n
On-Die Termination (ODT)
Asynchronous ODT
Intel
®
Fast Memory Access (Intel
®
FMA):
- Just-in-Time Command Scheduling
- Command Overlap
- Out-of-Order Scheduling
The memory channels are named as Channel A and Channel B.

Table of Contents

Other manuals for Intel S1200V3RP

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Intel S1200V3RP and is the answer not in the manual?

Intel S1200V3RP Specifications

General IconGeneral
BrandIntel
ModelS1200V3RP
CategoryServer Board
LanguageEnglish

Related product manuals