10-8 Limit Tests
If the handler requires a low-going EOT pulse, line #4 of the digital output must initially be
set high. When the EOT line is pulsed low, the binning operation occurs. When using the CON-
FIG LIMITS MENU to define pass/fail bit patterns, line #4 must be set low. If, for example, the
required fail pattern by the handler is HI, LO, HI, then you must define the fail pattern of the test
to be HI, LO, HI, LO. When the test fails, the HI, LO, HI bit pattern is sent to the handler. When
line #4 goes LO, the bit pattern is latched into the register of the handler, and the binning oper-
ation occurs.
Conversely, if the handler requires a high-going EOT pulse, the EOT line of the digital output
must initially be set low (off). When the EOT line is pulsed high, the binning operation occurs.
Line 4 mode
When using a category pulse component handler, Model 6514 must be set to the Busy or
/Busy mode. In the Busy mode, the idle state for line 4 is LO. When the test starts (SOT line
pulsed), line 4 goes HI (busy state). After the test is finished, it goes back to LO. For the /Busy
mode, the idle state for line 4 is HI and busy state is LO.
When using a catagory register component handler, Model 6514 must be set for the End of
Test mode. In this mode, Model 6514 sends the EOT pulse to the component handler as previ-
ously explained.
Digital output clear pattern
After every binning operation, the digital output needs to be reset to a clear pattern, which
serves as a "no action" condition for the component handler.
Model 6514 can be programmed to automatically clear the digital output after the pass or fail
pattern is sent. With auto-clear, you must specify the required pulse width (delay) for the pass
or fail pattern. When not using auto-clear, you must return the digital output to its clear pattern.
NOTE With the Busy line 4 mode selected, the clear state of line 4 is LO, regardless of the
configured clear pattern. With the /Busy mode selected, the clear state of line 4 is HI.
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