Kyocera FS-C8500DN - Page 317

2KA
2-3-19
YC30 1 +5V1 O 5 V DC 5 V DC power to HVCPWB
Connected to
the high volt-
age control
PWB
2 +5V1 O 5 V DC 5 V DC power to HVCPWB
3SGND -- Ground
4SGND -- Ground
5 PWB SCLK BUF O 0/3.3 V DC (pulse) HVCPWB clock signal
6 PWB SDI BUF I 0/3.3 V DC (pulse) HVCPWB serial communication data signal
7 PWB SDO BUF O 0/3.3 V DC (pulse) HVCPWB serial communication data signal
8 HVU SEL BUF O 0/3.3 V DC HVCPWB select signal
9 PWB RDY BUF I 0/3.3 V DC HVCPWB ready signal
10 DLP1 HV REM O 0/3.3 V DC Developing bias M: On/Off
11 DLP2 HV REM O 0/3.3 V DC Developing bias C: On/Off
12 DLP3 HV REM O 0/3.3 V DC Developing bias Y: On/Off
13 DLP4 HV REM O 0/3.3 V DC Developing bias K: On/Off
YC35 1 +24V1 - - Not used
Connected to
the eject
PWB
2 SGND - - Not used
3 SGND - - Not used
4 MCV_ENBL - - Not used
5 FGND - - Not used
6
MCV_FED_COUNT O 0/24 V DC FSSOL2: On/Off (ACT)
7 MCV_EJ_COUNT O 0/24 V DC FSSOL2: On/Off (REV)
8 MCV_COPY_SIG - - Not used
9 MCV_UART_TXD - - Not used
10 SGND - - Not used
11 MCV_UART_RXD - - Not used
12 SGND - - Not used
YC38 1 LSU FAN REM O 0/24 V DC LSUFM: On/Off
Connected to
the LSU fan
motor and
inner temper-
ature sensor
1
2 +24V1 O 24 V DC 24 V DC power to LSUFM
3SGND -- Ground
4 POLYGON TEMP I Analog INTEMS1 detection signal
YC39 1 +24V1 O 24 V DC 24 V DC power to DEVFM5
Connected to
the develop-
ing fan motor
5
2 SIDE_DLP_FAN O 0/24 V DC DEVFM5: On/Off
Connector Pin No. Signal I/O Voltage Description