Lime Microsystems LMS7002MR3 - Page 61

57
Address (15 bits)
Bits
Description
0x0098
15 – 9
8
7
6
5
4
3
2
1
0
Reserved
SPDUP_LDO_AFE: Short the noise filter resistor to speed up the settling time
0 – noise filter resistor in place (default)
1 – Noise filter resistor bypassed
should be connected to a 1~5uS at the power up
SPDUP_LDO_CPGN: Short the noise filter resistor to speed up the settling time
0 – noise filter resistor in place (default)
1 – Noise filter resistor bypassed
should be connected to a 1~5uS at the power up
SPDUP_LDO_CPSXR: Short the noise filter resistor to speed up the settling time
0 – noise filter resistor in place (default)
1 – Noise filter resistor bypassed
should be connected to a 1~5uS at the power up
SPDUP_LDO_CPSXT: Short the noise filter resistor to speed up the settling time
0 – noise filter resistor in place (default)
1 – Noise filter resistor bypassed
should be connected to a 1~5uS at the power up
SPDUP_LDO_DIG: Short the noise filter resistor to speed up the settling time
0 – noise filter resistor in place (default)
1 – Noise filter resistor bypassed
should be connected to a 1~5uS at the power up
SPDUP_LDO_DIGGN: Short the noise filter resistor to speed up the settling time
0 – noise filter resistor in place (default)
1 – Noise filter resistor bypassed
should be connected to a 1~5uS at the power up
SPDUP_LDO_DIGSXR: Short the noise filter resistor to speed up the settling time
0 – noise filter resistor in place (default)
1 – Noise filter resistor bypassed
should be connected to a 1~5uS at the power up
SPDUP_LDO_DIGSXT: Short the noise filter resistor to speed up the settling time
0 – noise filter resistor in place (default)
1 – Noise filter resistor bypassed
should be connected to a 1~5uS at the power up
SPDUP_LDO_DIVGN: Short the noise filter resistor to speed up the settling time
0 – noise filter resistor in place (default)
1 – Noise filter resistor bypassed
should be connected to a 1~5uS at the power up
Default: 00000000 00000000
0x0099
15 – 8
7 – 0
RDIV_VCOSXR[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio. Default: 101
Vout=860mV+3.92mV *RDIV
RDIV_VCOSXT[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio. Default: 101
Vout=860mV+3.92mV *RDIV
Default: 01100101 01100101
0x009A
15 – 8
7 – 0
RDIV_TXBUF[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio. Default: 101
Vout=860mV+3.92mV *RDIV
RDIV_VCOGN[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio. Default: 140
Vout=860mV+3.92mV *RDIV
Default: 01100101 10001100
0x009B
15 – 8
7 – 0
RDIV_TLOB[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio. Default: 101
Vout=860mV+3.92mV *RDIV
RDIV_TPAD[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio. Default: 101
Vout=860mV+3.92mV *RDIV
Default: 01100101 01100101
0x009C
15 – 8
7 – 0
RDIV_TIA12[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio. Default: 101
Vout=860mV+3.92mV *RDIV
RDIV_TIA14[7:0]:Controls the output voltage of the LDO by setting the resistive
voltage divider ratio. Default: 140
Vout=860mV+3.92mV *RDIV
Default: 01100101 10001100