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5.17 Debug Access

MIPS® Malta™ User’s Manual, Revision 01.07 43

J27

Odd

ARBITER Clock PCI_CLK 33.33 MHz (default)

15:8 PCI_REQN_CORE,

PCI_REQN_SOUTHBRIDGE,

PCI_REQN_ETHERNET,

PCI_REQN_AUDIO,

PCI_REQN_CON1,

PCI_REQN_CON2,

PCI_REQN_CON3,

PCI_REQN_CON4

Requests

7:0 PCI_GNTN_CORE,

PCI_GNTN_SOUTHBRIDGE,

PCI_GNTN_ETHERNET,

PCI_GNTN_AUDIO,

PCI_GNTN_CON1,

PCI_GNTN_CON2,

PCI_GNTN_CON3,

PCI_GNTN_CON4

Grants

Table 5.6 Logic Analyser Connectors (Continued)

Ref Function Bits Signals Description

Mips Technologies Malta - Page 43