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MPI 40 Series - Step in; Spindle Speed Control; Side Selection

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3.6.3.2 Step In
A
true
level
(OV
to
.4V) on
the
DIRECTION
SELECT
line
along
with
pulse(s)
on
the
STEP
line
will
move
the
read/write
heads
towards
the
center
of
the
disk.
3.6.4 Spindle Speed Control
The
spindle
servo
electronics
are
mounted on a
separate
circuit
board
located
at
the
right
rear
of
the
Drive
above
the
diskette
plane.
When
the
MOTOR
ON
signal
becomes
active
{logical
zero),
transistor
Ql {page 1
area
B7)
is
turned
off
and
Q2
is
turned
on,
gating
+24V
to
one
side
of
the
spindle
motor
coils.
Transistors
Q3, Q4, Q5, and
Q6
when
turned
on
simply
provide
a
ground
path
for
the
+24V
on
the
other
side
of
the
coils.
Only one
of
these
transistors
is
turned
on
at
a
time.
They
are
enabled
by
the
signals
HEl,
HEl,
HE2,
and
HE2
which
control
the
base
of
the
transistors
through
the
diodes
in
parallel.
When
both
diodes
in
parallel
are
reversed
biased,
the
transistor
sends
a
ground
to
one
side
of
the
coil
and
the
motor moves
to
that
phase.
When
the
enabled
phase
is
reached,
it
will
be
disabled
and
the
next
phase
enabled;
this
causes
the
motor
to
rotate.
The
four
control
signals
keep
changing
states
by
the
"Hall
Effect"
sensors
mounted
internal
to
the
motor.
The
four
comparators
of
U2
compare
the
sensor
outputs
and
develop
the
control
signals.
As
the
motor
rotates,
HEI
is
used
to
generate
a
pulse
train
at
Ul-1
which,
in
turn,
creates
a
voltage
level
at
the
charge
pump.
This
voltage
is
compared
with
a
reference
voltage
at
pin
10 and
if
it
is
less
than
the
reference
voltage,
the
motor
current
will
be
in-
creased
by
allowing
Ul-8
to
go more
positive
to
the
base
of
Q2
so
that
the
spindle
speed
will
be
increased.
If
the
motor
is
running
too
fast,
then
the
charge
pump
voltage
will
exceed
the
reference
voltage
(Ul-10)
and
the
motor
current
(Ul-8)
will
be
cut
off
which
in
turn
will
reduce
the
spindle
speed.
The
spindle
speed
control
servo
maintains
the
rotating
speed
of
the
motor
within
1-1/2%
of
its
nominal
speed.
3.6.5 Side Selection
In
a
standard
two
sided
drive,
head
selection
is
controlled
by
the
SIDE
SELECT
interface
line
(
Pl-14;
page
3,
area
CB)
A
false
or
high
level
(2.SV
to
5.25V)
on
the
SIDE
SELECT
line
will
select
the
read/
write
head
on
the
lower
side
(side
0)
of
the
disk
and a
true
or
low
level
{OV
to
.4V) on
the
SIDE
SELECT
line
will
select
the
read/
write
head
on
the
upper
side
(side
1)
of
the
disk.
SIDE
SELECT
is
inverted
by U27-8 {page
3,
area
C7)
and
routed
to
page
2,
area
C8
as
+
Side
Select.
When
selecting
head
~,
the
+
Side
Select
signal
would be a low
level.
Through
inverter
U20-8,
it
is
ANDed
with
+
Erase
to
turn
on
the
erase
circuit
for
head
~.
The
high
level
at
U20-8
(area
B8)
is
sent
through
open-collector
Ul-10
3-20

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