Vector-LP Radio Beacon Transmitter Technical Instruction Manual Page 6-7
Section 6 Theory of Operation Issue 1.1
6.4.2.1.1 DDS Control Information
The RF carrier frequency is set using five
binary coded decimal (BCD) switches (S1
through S5). When a current-sink-to-ground
is applied at the Reset DDS input, or during
turn on, the microprocessor monitors these
switches and outputs the appropriate 48-bit
value to the DDS Frequency Tuning Word
#1 register. The 48-bit value is written in six
consecutive bytes to the DDS's six internal
registers. The sclk signal is enabled on each
write cycle.
6.4.2.1.2 N Divider Control Information
The 4g
C
/B frequency is divided by an 'N'
factor to provide 2g
PDM
output frequency
between 126 kHz and 134 kHz (when E3 is
set in
LOW PDM mode) or between 245 kHz
and 276 kHz (when E3 is set in
HIGH PDM
mode) (see formula below). The
microprocessor determines the value of N
and outputs the information at pins 2, 3, 4, 5,
6 and 7. The N divider circuit uses this
information as the N dividing factor.
- for
PDM
= 130 kHz (HIGH PDM position):
g
C
and g
PDM
are expressed in kHz
»
¼
º
«
¬
ª
g
g
g
130
652
int
4
2
C
C
PDM
6.4.2.2 DIRECT DIGITAL SYNTHESIZER
The direct digital synthesizer consists of
integrated circuit U5 (AD98525Q) and
associated components. It generates a
frequency of 4g
C
based on information
provided by microprocessor U4 (refer to
paragraph 6.5.2.1). Integrated circuit U5 is a
CMOS, numerically controlled oscillator with
a 48-bit phase accumulator and 12-bit
digital-to-analog converter (DAC). The
phase accumulator, which is responsible for
generating an output frequency, is presented
with a 48-bit value from the Frequency
Tuning Word 1 registers, whose contents
determine the FTW as follows:
The 10 MHz clock input is coupled with U5's
internal programmable reference clock
multiplier. This results in a system clock of
50 MHz (i.e., SYSCLK = 50 MHz).
The 12-bit output from the phase
accumulator is input to the DAC, which
outputs a stepped sine wave at 4gc. The 4gc
output is then low-pass filtered to remove
high frequency components.
6.4.2.3 LOW PASS FILTER
A low-pass filter consisting of C21, L1, and
C23 removes the high frequency images
present in the DDS output signal. The output
is a sine wave at a frequency of 4g
C
.
6.4.2.4 DIGITIZER
The output of the low-pass filter is connected
to a digitizer circuit consisting of transistor
Q4, inverter U10:B, and associated
components. Inverter U10:B outputs an
approximate square wave at a frequency of
4g
C
, which is applied to a y4 circuit and to
the N divider circuit.
6.4.2.5 IPM CORRECTION
Not applicable to Vector transmitters.
6.4.2.6 WAVEFORM SYMMETRY
RF DRIVE SYMMETRY potentiometer R32
is adjusted for an RF drive output waveform,
which is a symmetrical square wave (50%
duty cycle). The position of SYMMETRY
ADJ shorting jumper E6 determines when
the RF drive symmetry circuit is enabled or
disabled. E6 should be installed in the
ENABLE position (shorting pins 1 and 2)
when used in a Vector transmitter.
SYSCLK
cyxputFrequenDesiredOutFTW )
48
2(
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