Vector-LP Radio Beacon Transmitter Technical Instruction Manual Page 6-17
Section 6 Theory of Operation Issue 1.1
6.5.1.2.1 Ac Supply Voltage
The Ac Power input (J4-21) is an
unregulated dc voltage that is proportional to
the ac source. The input is filtered and
compared to the low ac ref fault threshold on
operational amplifier U4C. If the Ac Power
voltage is below this threshold, the ac low
signals switch to 0 V. The Carrier Ref (A)
and (B) outputs clamp to 0 V and the
Shutback (A) (J7 1) and (B) (J7-2) outputs
switch to 0 V and inhibit the exciter’s
modulator drive. The transmitter's RF output
turns off (shuts back) and remains off until
the ac power returns to an acceptable
voltage. The system diagram’s AC Mains
lamp displays a fault condition. An Ac
Sample signal is applied to ADC U9 for
application to the diagnostic display.
6.5.1.2.2 Reflected Power Monitor
The Refld Pwr Sample input (J1-5) is a dc
voltage that is proportional to the reflected
power at the transmitter's output. The input is
filtered and buffered by operational amplifier
U1B and associated components, and then
applied to the remote interface PWB via the
external serial interface (microcontroller U22).
The signal is also compared to a pre-
determined refld pwr shtbk ref fault threshold
on operational amplifier U4A. When the
reflected power indicates a VSWR of greater
than 2:1, relative to rated forward power, the
refld pwr sample input exceeds the fault
threshold and the refld_pwr_shutback signal
switches to 5 V. The Carrier Ref (A) and (B)
outputs clamp to 0 V and the Shutback (A)
(J7-1) and (B) (J7-2) outputs switch to 0 V
and inhibit the exciter’s modulator drive. A
clock pulse is also applied to an alarm count/
cutback circuit in complex programmable
logic device (CPLD) U18. The RF output is
instantly shut back (turn off). The system
diagram’s Output Network lamp displays a
fault condition. A Refld Pwr Sample signal is
applied to ADC U9 for application to the front
panel’s diagnostic display.
Turning off the RF output reduces the refld
pwr sample input to 0 V. The Carrier Ref (A)
and (B) outputs are restored to their
pre-shutback levels, the Shutback A and B
outputs return to open collector, and the RF
output is restored at an exponential rate. If
the fault threshold is exceeded before the
pre-set power level is reached, the shutback
cycle is repeated. If two or more shutback
cycle clock pulses are applied within any two
second period, the Carrier Ref outputs are cut
back (reduced) until the carrier level is cut
back to a level that results in an acceptable
reflected power. When the transmitter enters
cutback mode, the system diagram’s Output
Network lamp flashes on and off. When the
refld pwr sample input returns to or is
maintained at a level which is less than the
fault threshold, the Shutback outputs returns
to open collector but the system diagram’s
Output Network lamp continues to display a
fault as a maintenance aid. The lamp remains
on until reset by the diagnostic display menu.
6.5.1.3 SAMPLE MONITORING CIRCUITS
In addition to the parameters described in
paragraph 6.5.6.2, various parameters are
applied to the control/display PWB for local
(via the front panel’s diagnostic display) and
external (via the remote interface PWB)
monitoring. In some cases, these parameters
have associated alarm detection circuitry, but
it is not resident on the control/display PWB.
6.5.1.3.1 PDM Drive
The PDM (A) (J4-9) and PDM (B) (J4-7)
inputs are pulses which represent the PDM
signal applied to RF power modules A and B.
The inputs are filtered through operational
amplifiers U7B and U11B and associated
components. PDM (A) Sample and PDM (B)
Sample signals are applied to ADC U9 for
application to the front panel’s diagnostic
display.
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