LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 2.1 — 9 May 2018 52 of 105
NXP Semiconductors
LPC5411x
32-bit ARM Cortex-M4/M0+ microcontroller
[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), 3.3V.
[2] Characterized through bench measurements using typical samples.
[3] Clock source FRO. PLL disabled. All SRAM powered. Compiler settings: Keil µVision 5.17., optimization level 0, optimized for time off.
Conditions: VDD = 3.3 V; Tamb = 25 °C; active mode; all peripherals disabled; BOD disabled; Prefetch disabled in FLASHCFG
register. See the FLASHCFG register in the LPC5411x, UM10914 User Manual for system clock flash access time settings.
SRAM0 and SRAMX powered. SRAM1 and SRAM2 powered down. Measured with Keil uVision 5.17. Optimization level 0,
optimized for time OFF.
12 MHz, 48 MHz, and 96 MHz: FRO enabled; PLL disabled.
24 MHz, 36 MHz, 60 MHz, 72 MHz, 84 MHz, and 100 MHz: FRO enabled; PLL enabled.
Fig 10. CoreMark power consumption: typical A/MHz for M4 and M0+ cores
DDD
)UHTXHQF\0+]
$0+]
$0+]$0+]
0)/$6+0)/$6+0)/$6+
065$0
065$0065$0
0)/$6+
0)/$6+0)/$6+
065$0
065$0065$0
Table 15. Static characteristics: Power consumption in sleep mode
T
amb
=
40
C to +105
C, unless otherwise specified.1.62 V
V
DD
3.6 V.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
ARM Cortex-M4 in sleep mode; ARM Cortex-M0+ in sleep mode
I
DD
supply current CCLK = 12 MHz
[2][3]
-900-A
CCLK = 48 MHz
[2][3]
-1.6-mA
CCLK = 96 MHz
[2][3]
-3.0-mA
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