LPC5411x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 2.1 — 9 May 2018 69 of 105
NXP Semiconductors
LPC5411x
32-bit ARM Cortex-M4/M0+ microcontroller
Master; 1.62 V VDD 2.0 V
t
v(Q)
data output valid time on pin I2Sx_TX_SDA
[2]
CCLK = 1 MHz to 12 MHz 32.7 - 56.6 ns
CCLK = 48 MHz to 60 MHz 29.9 - 48.9 ns
CCLK = 96 MHz 29.0 - 47.2 ns
on pin I2Sx_WS
CCLK = 1 MHz to 12 MHz 35.1 - 61.1 ns
CCLK = 48 MHz to 60 MHz 31.9 - 51.8 ns
CCLK = 96 MHz 31.0 - 49.7 ns
t
su(D)
data input set-up time on pin I2Sx_RX_SDA
[2]
CCLK = 1 MHz to 12 MHz 0.0 - - ns
CCLK = 48 MHz to 60 MHz 0.0 - - ns
CCLK = 96 MHz 0.0 - - ns
t
h(D)
data input hold time on pin I2Sx_RX_SDA
[2]
CCLK = 1 MHz to 12 MHz 0.0 - - ns
CCLK = 48 MHz to 60 MHz 0.0 - - ns
CCLK = 96 MHz 0.0 - - ns
Slave; 1.62 V VDD 2.0 V
t
v(Q)
data output valid time on pin I2Sx_TX_SDA
[2]
CCLK = 1 MHz to 12 MHz 25.8 - 47.0 ns
CCLK = 48 MHz to 60 MHz 23.0 - 38.9 ns
CCLK = 96 MHz 22.2 - 37.1 ns
t
su(D)
data input set-up time on pin I2Sx_RX_SDA
[2]
CCLK = 1 MHz to 12 MHz 0.0 - - ns
CCLK = 48 MHz to 60 MHz 0.0 - - ns
CCLK = 96 MHz 0.0 - - ns
on pin I2Sx_RX_WS
CCLK = 1 MHz to 12 MHz 0.0 - - ns
CCLK = 48 MHz to 60 MHz 0.0 - - ns
CCLK = 96 MHz 0.0 - - ns
t
h(D)
data input hold time on pin I2Sx_RX_SDA
[2]
CCLK = 1 MHz to 12 MHz 1.0 - - ns
CCLK = 48 MHz to 60 MHz 1.0 - - ns
CCLK = 96 MHz 1.0 - - ns
on pin I2Sx_RX_WS
CCLK = 1 MHz to 12 MHz 2.0 - - ns
CCLK = 48 MHz to 60 MHz 2.0 - - ns
CCLK = 96 MHz 2.0 - - ns
Table 30. Dynamic characteristics: I
2
S-bus interface pins
[1][4]
T
amb
=
40
C to 105
C; V
DD
= 1.62 V to 3.6 V; C
L
= 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.
Symbol Parameter Conditions Min Typ
[3]
Max Unit
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