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Interrupt Tasks Section 4-3
Problems may occur with data concurrency even if DI(693) and EI(694) are
used to disable interrupt tasks during execution of an instruction that requires
response reception and processing (such as a network instruction or serial
communications instruction).
Note Execution of the BIT COUNTER (BCNT), BLOCK SET (BSET), and BLOCK
TRANSFER (XFER) instructions will not be interrupted for execution of inter-
rupt task, i.e., execution of the instruction will be completed before the inter-
rupt task is executed, delaying the response of the interrupt. To prevent this,
separate data processing for these instructions into more than one instruc-
tions, as shown below for XFER.
Cyclic task
Reading and writing I/O
memory common to
interrupt tasks.
Processing with interrupt task
execution enabled
Disabled
Enabled
Interrupt task
Interrupt task
XFER
&50
D00050
D30050
XFER
&50
D00000
D30000
XFER
&100
D00000
D30000
Interrupts are possible as
soon as execution of XFER
has been completed.
XFER instruction is
not interrupted.
Processing
separated.
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