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Basic Concepts Section 2-1
Downwardly Differentiated Instructions (Instruction preceded by %)
• Output instructions: The instruction is executed only during the cycle in
which the execution condition turned OFF (ON → OFF) and is not exe-
cuted in the following cycles.
■ Timing Chart
• Input Instructions (Logical Starts and Intermediate Instructions): The
instruction reads bit status, makes comparisons, tests bits, or perform
other types of processing every cycle and will output the execution condi-
tion (power flow) when results switch from ON to OFF. The execution con-
dition will turn OFF the next cycle.
■ Timing Chart
Note Unlike the upwardly differentiated instructions, downward differentia-
tion variation (%) can only be added to LD, AND, OR, SET and RSET
instructions. To execute downward differentiation with other instruc-
tions, combine the instructions with a DIFD or a DOWN instruction.
NOT can be added to instructions only when using a CS1-H, CJ1-H,
CJ1M, or CS1D CPU Unit.
• Input Instructions (Logical Starts and Intermediate Instructions): The
instruction reads bit status, makes comparisons, tests bits, or perform
other types of processing every cycle and will output an OFF execution
Example
%SET
Executes the SET instruction once
when CIO 000102 goes ON to OFF.
(%) Downwardly dif-
ferentiated instruction
Bit A
Bit A
Operation
of SET
%SET
Example
Downwardly differentiated instruction
Will turn ON when the CIO 000103 switches from
ON → OFF and will turn OFF after one cycle.
Bit A
Bit A
Bit B
Bit B
1 cycle
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