Profichip VPC3+S - Page 100

8 Hardware Interface
100
Revision 1.04
VPC3+S User Manual
Copyright © profichip GmbH, 2012
WRITE Sequence
Following the START condition from the master, Slave Address (6 bits) and
the R/W bit (which is a logic low) are clocked onto the bus by the master
transmitter. This indicates to the addressed slave receiver that the address
high byte will follow once it has generated an Acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted by the master is the
high-order byte of the address and will be written into the Address Pointer
of the VPC3+S. The next byte is the Least Significant Address Byte. After
receiving another Acknowledge signal from the VPC3+S, the master device
will transmit the data byte to be written into the addressed memory location.
The VPC3+S acknowledges again and the master either generates a STOP
condition or transfers more data bytes to the VPC3+S. Upon receipt of each
data byte, the VPC3+S generates an Acknowledge signal and the internal
Address Pointer is incremented by ‘1’. When the highest address is
reached (0x7FF in case of 2 kB RAM mode or 0xFFF in 4 kB mode), the
address counter rolls over to address 0x000 allowing the write sequence to
be continued indefinitely. The write operation is terminated by receiving a
STOP condition from the master.
0
X X X X 11 10 9 8
Control Byte Address High Byte
S
A
C
K
S
T
A
R
T
A
C
K
7 6 5 4 3 2 1 0
Address Low Byte
A
C
K
7 6 5 4 3 2 1 0
Data Byte 0
A
C
K
7 6 5 4 3 2 1 0
Data Byte n
A
C
K
P
S
T
O
P
Figure 8-16: I2C WRITE Sequence
READ Operations
Read operations are initiated in the same way as write operations, with the
exception that the R/W bit of the control byte is set to ‘1’. There are three
basic types of read operations: current address read, random read and
sequential read.
Current Address READ Operation
The VPC3+S contains an address counter that maintains the address of the
last byte accessed, internally incremented by ‘1’. Therefore, if the previous
read access was to address ‘n’ (n is any legal address), the next current
address read operation would access data from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’, the VPC3+S issues
an acknowledge and transmits the 8-bit data byte. The master will not
acknowledge the transfer, but does generate a STOP condition and the
VPC3+S discontinues transmission.