Profichip VPC3+S - Page 94

8 Hardware Interface
94
Revision 1.04
VPC3+S User Manual
Copyright © profichip GmbH, 2012
This process continues for a total of 16 edges on the SCK line with data
being latched on even numbered edges and shifting taking place on odd
numbered edges.
Data reception is double buffered, data is serially shifted into the SPI shift
register during the transfer and is transferred to the parallel SPI Data
Register after the last bit is shifted in.
Principles of Operation
The VPC3+S contains an 8-bit instruction register and a 16-bit address
register. The device is accessed via the MOSI pin, with data being clocked
in on the configured edge of SCK. The XSS pin must be held low for the
entire operation.
The first byte received during a valid SPI transfer is interpreted as SPI
instruction. Figure 8-6 lists the supported instruction bytes and formats for
the device operation. All instructions, addresses, and data are transferred
MSB first, LSB last.
Instruction
Name
Instruction
Format
Description
READ BYTE
0001 0011
Read a single data byte from selected address
READ ARRAY
0000 0011
Read several data bytes beginning at selected
address (with auto-increment)
WRITE BYTE
0001 0010
Write a single data byte to selected address
WRITE ARRAY
0000 0010
Write several data bytes beginning at selected
address (with auto-increment)
Figure 8-6: SPI Instruction Set
Note:
In SPI interface mode all internal addresses are interpreted in Intel format.
Motorola format (byte swapping for certain addresses) is not supported in
SPI mode.
READ BYTE Sequence
The device is selected by pulling XSS low. The 8-bit READ BYTE
instruction is transmitted to the VPC3+S followed by the 16-bit address,
with the four MSBs of the address being “don’t care” bits (in case of 2 kB
RAM mode the five MSBs of the address are “don’t care”).
After the correct READ BYTE instruction and address are sent, the data
byte stored in the memory at the selected address is shifted out on the
MISO pin. After additional 8 SCK pulses the complete data byte has sent
and no more valid data bits are shifted out on the MISO pin. There is no
auto-increment mechanism for this instruction. The read operation is
terminated by raising the XSS pin (Figure 8-7).