R8C/20 Group, R8C/21 Group 14. Timers
Rev.2.00 Aug 27, 2008 Page 255 of 458
REJ09B0250-0200
• Select with the CMD1 to CMD0 bits for the data transfer timing from the buffer register to the general
register. However, transfer with the following timing in spite of the value of the CMD1 to CMD0 bits for
the following cases:
Value in buffer register ≥ Value in TRDGRA0 register:
Transfer at the underflow in the TRD1 register.
And then, when setting the buffer register to 0001h or above and the smaller value than the one in the
TRDGRA0 register, and the TRD1 register underflows in the fist time after setting, the value is transferred
to the general register. After that, transfer the value with the timing selected by the CMD1 to CMD0 bits.
Figure 14.112 Operation When Value in Buffer Register ≥ Value in TRDGRA0 Register in
Complementary PWM Mode
0000h
TRDGRD0 register
TRDIOB0 output
n3
n2
m + 1
n3
n2
n1
n2 n1
n3
n2 n2 n1n1TRDGRB0 register
Transfer
Transfer by
underflow in TRD1
register because of
n3 > m
Transfer by
underflow in TRD1
register because
of first setting to
n2 < m
TRDIOD0 output
m: Setting Value in TRDGRA0 Register
The above applies to the following conditions:
• The CMD1 to CMD0 bits in the TRDFCR register are set to 11b.
(Data in the buffer register is transferred at the compare match in the TRD0 and TRDGRA0 registers in complementary
PWM mode.)
• Both the OSL0 and OLS1 bits in the TRDFCR are set to 1. (active ‘H” for normal-phase and counter-phase)
Count value in TRD0
register
Count value in TRD1
register
Transfer with timing set by
CMD1 to CMD0 bits
Transfer with timing set by
CMD1 to CMD0 bits
Transfer
Transfer Transfer
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