R8C/20 Group, R8C/21 Group 14. Timers
Rev.2.00 Aug 27, 2008 Page 261 of 458
REJ09B0250-0200
Figure 14.117 TRECR1 Register in Output Compare Mode
Figure 14.118 TRECR2 Register in Output Compare Mode
Timer RE Control Register 1
Symbol Address After Reset
TRECR1
011Ch 00h
Bit Symbol Bit Name Function RW
b3 b2
INT
b1 b0
0
—
(b0)
b7 b6 b5 b4
00
—
TCSTF RO
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RE count status flag 0 : During count stop
1 : In count
TREO pin output enable bit 0 : Disable clock output
1 : Enable clock output
TOENA RW
RW
TSTART
Timer RE count start bit 0 : Count stops
1 : Count starts
RW
—
(b6-b5)
Reserved bit Set to 0
TRERST
Timer RE reset bit When setting this bit to 0 after setting it to
1, the follow ings w ill occur.
• The TRESEC, TREMIN, and TRECR2
registers are set to 00h.
• The TCSTF, INT, and TSTART bits in the
TRECR1 register are set to 0.
• The 8-bit counter is set to 00h and
the 4-bit counter is set to 0h.
RW
RW
Interrupt request timing bit Set to 0 in output compare mode
Timer RE Control Register 2
Symbol Address After Reset
TRECR2
011Dh 00h
Bit Symbol Bit Name Function RW
b3 b2 b1 b0
0000
0 : Disable compare match interrupt
1 : Enable compare match interrupt
—
(b4-b0)
b7 b6 b5 b4
0
RW
Reserved bit Set to 0
COMIE
Compare match interrupt enable bit
RW
—
(b7-b6)
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
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