R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface
Rev.2.00 Aug 27, 2008 Page 306 of 458
REJ09B0250-0200
16.2.6.2 Data Transmission
Figure 16.19 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Transmission (4-Wire Bus Communication Mode). During the data transmit, the clock synchronous serial I/O
with chip select operates as described below.
When the clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock
and data. When the UUSA is set as a slave device, it outputs data in synchronized with the input clock while
“L” applies to the SCS
pin.
When writing the transmit data to the SSTDR register after setting the TE bit to 1 (enables transmit), the TDRE
bit is automatically set to 0 (data is not transferred from the SSTDR to SSTRSR registers) and the data is
transferred from the SSTDR to SSTRSR registers. After the TDRE bit is set to 1 (data is transferred from the
SSTDR to SSTRSR registers), a transmit is started. When the TIE bit in the SSER register is set to 1, the TXI
interrupt request is generated.
When the 1-frame data is transferred while the TDRE bit is set to 0, the data is transferred from the SSTDR to
SSTRSR registers and the next frame transmit is started. If the 8th bit is transmitted while the TDRE is set to 1,
the TEND in the SSSR register is set to 1 (when the last bit of the transmit data is transmitted, the TDRE bit is
set to 1) and the state is retained. If the TEIE bit in the SSER register is set to 1 (enables transmit-end interrupt
request), the TEI interrupt request is generated. The SSCK pin is retained “H” after transmit-end and the SCS
pin is held “H”. When the SCS pin is transmitted When transmitting continuously while the SCS pin is held
“L”, write the next transmit data to the SSTDR register before transmitting the 8th bit.
Transmit can not be performed while the ORER bit in the SSSR register is set to 1 (overrun error occurs).
Confirm that the ORER bit is set to 0 before transmit.
The difference from the clock synchronous communication mode is that the SSO pin is placed in high-
impedance state while the SCS
pin is placed in high-impedance state when operating as a master device and the
SSI pin is placed in high-impedance state while the SCS
pin is placed in “H” input state when operating as a
slave device.
A sample flowchart is the same as the clock synchronous communication mode (refer to Figure 16.14 Sample
Flowchart of Data Transmission (Clock Synchronous Communication Mode)).
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