R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface
Rev.2.00 Aug 27, 2008 Page 308 of 458
REJ09B0250-0200
16.2.6.3 Data Reception
Figure 16.20 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Reception (4-Wire Bus Communication Mode). During the data receive, the clock synchronous serial I/O with
chip select operates as described below.
When the clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock
and inputs data. When the clock synchronous serial I/O with chip select is set as a salve device, it outputs data
synchronized with the input clock while the SCS
pin is held “L” input. When the clock synchronous serial I/O
with chip select is set as a master device, it outputs a receive clock and starts receiving by performing dummy
read on the SSRDR register.
After the 8-bit data is received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (enables RXI and
OEI interrupt request), the RXI interrupt request is generated. If the SSRDR register is read, the RDRF bit is
automatically set to 0 (no data in the SSRDR register).
Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1-byte data, the
receive operation is completed). The clock synchronous serial I/O with chip select outputs a clock for receiving
8-bit data and stops. After that, set the RE bit in the SSER register to 0 (disables receive) and the RSSTP bit to
0 (receive operation is continued after receiving 1-byte data) and read the receive data. If the SSRDR register is
read while the RE bit is set to 1 (enables receive), a receive clock is output again.
When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun
error occurs: OEI) and the operation is stopped. When the ORER bit is set to 1, receive can not be performed.
Confirm that the ORER bit is set to 0 before restarting receive.
When the RDRF and ORER bits are set to 1, it varies depending on setting the CPHS bit in the SSMR register.
Figure 16.20 shows when the RDRF and ORER bits are set to 1.
When the CPHS bit is set to 1 (data download at the odd edges), the RDRF and ORER bits are set to 1 at one
point of a frame.
A sample flowchart is the same as the clock synchronous communication mode (refer to Figure 16.16 Sample
Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode)).
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