Renesas R8C/20

R8C/20 Group, R8C/21 Group 17. Hardware LIN
Rev.2.00 Aug 27, 2008 Page 354 of 458
REJ09B0250-0200
Figure 17.9 Example of Header Field Reception Flowchart (2)
Timer RA Set to start a pulse width measurement
TSTART bit in the TRACR register
← 1
Timer RA Read the count status flag
TCSTF flag in the TRACR register
Hardware LIN Set to start Synch Break detection
LSTART bit in the LINCR register
← 1
Hardware LIN Read the RXD0 input status flag
RXDSF flag in the LINCR register
A
TCSTF = 1?
YES
RXDSF = 1?
YES
NO
NO
Timer RA waits until the timer
starts counting.
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break
detection, Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in the LINST
register
← 1
Hardware LIN Read the Synch Break detection flag
SBDCT flag in the LINST register
SBDCT = 1?
YES
NO
B
Hard ware LIN detect a Synch
Break.
The interrupt of timer RA may be
used.
When Synch Break is detected,
timer RA is reloaded with the initially
set count value.
Even if the duration of the input “L”
level is shorter than the set period,
timer RA is reloaded with the initially
set count value and waits until the
next “L” level is input.
One to two cycles of the CPU clock
are required after Synch Break
detection before the SBDCT flag is
set to 1.
When the SBE bit in the LINCR
register is set to 0 (Unmasked after
Synch Break is detected), timer RA
may be used in timer mode after the
SBDCT flag in the LINST register is
set to 1 and the RXDSF flag in the
LINCR register is set to 0.
Hard ware LIN wait until the RXD0
input for UART0 is masked.
Do not apply “L” level to the RXD pin
until the RXDSF flag reads 1 after
writing 1 to the LSTART bit. This is
because the signal applied during
this time is input directly to UART0.
One to two cycles of the CPU clock
and zero to one cycle of the timer
RA count source are required after
the LSTART bit is set to 1 before the
RXDSF flag is set to 1.
After this, input to timer RA and
UART0 is enabled.
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the
TCSTF flag is set to 1.