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REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual
0.20 Jun 28, 2006 205 Figure 14.70 Registers TRDSR0 to TRDSR1 in PWM Mode revised.
212 Table 14.29 Reset Synchronous PWM Mode Specifications revised.
213 Figure 14.78 TRDSTR Register in Reset Synchronous PWM Mode
revised.
214 Figure 14.79 Registers TRDMR and TRDFCR in Reset Synchronous
PWM Mode revised.
215 Figure 14.80 Registers TRDOER1 to TRDOER2 in Reset Synchronous
PWM Mode;
NOTE in the TRDOER2 register added.
216 Figure 14.81 TRDCR0 Register in Reset Synchronous PWM Mode
revised.
217 Figure 14.82 Registers TRDSR0 to TRDSR1 in Reset Synchronous
PWM Mode revised.
223 Figure 14.88 TRDSTR Register in Complementary PWM Mode revised.
224 Figure 14.89 TRDMR Register in Complementary PWM Mode revised.
225 Figure 14.90 TRDFCR Register in Complementary PWM Mode revised.
226 Figure 14.91 Registers TRDOER1 to TRDOER2 in Complementary
PWM Mode;
NOTE in the TRDOER2 register added.
227 Figure 14.92 Registers TRDCR0 to TRDCR1 in Complementary PWM
Mode revised.
228 Figure 14.93 Registers TRDSR0 to TRDSR1 in Complementary PWM
Mode revised.
231
Below the Table 14.32;
“Since values ~ (buffer register).” added.
235 Figure 14.99 Block Diagram of PWM3 Mode
;
“Buffer” added.
236 Table 14.33 PWM3 Mode Specifications revised.
237 Figure 14.100 TRDSTR Register in PWM3 Mode revised.
238 Figure 14.101 Registers TRDMR and TRDFCR in PWM3 Mode revised.
239 Figure 14.102 Registers TRDOER1 to TRDOER2 in PWM3 Mode;
NOTE in the TRDOER2 register added.
241 Figure 14.104 TRDCR0 Register in PWM3 Mode revised.
242 Figure 14.105 Registers TRDSR0 and TRDSR1 in PWM3 Mode added.
243 Figure 14.106 Registers TRDIER0 and TRDIER1 in PWM3 Mode
revised.
245 Table 14.34 TRDGRji Register Functions in PWM3 Mode
revised.
On the 4th line from the bottom;
“Registers TRDGRC0, ~ (buffer register).” added.
246 Figure 14.109 Operating Example of PWM3 Mode revised.
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