C - 8
REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual
0.20 Jun 28, 2006
249 14.3.12 Notes on Timer RD;
“14.3.13 Precautions on Timer RD” → “
14.3.12 Notes on Timer RD
”
revised.
14.3.12.1 TRDSTR Register (i = 0 or 1) added.
250 14.3.12.6 Reset Synchronous PWM Mode revised.
14.3.12.7 Complementary PWM Mode revised.
254 14.3.13.7 PWM3 mode deleted.
14.3.12.8 Count Source fOCO40M added.
255 14.4 Timer RE, on the 3rd line;
“The count source ~ timer operations.” added.
262 14.4.2 Notes on Timer RE;
“
14.4.2 Precautions on Timer RE
” → “
14.4.2 Notes on Timer RE
” revised.
267 Figure 15.5 Registers UiC0 and UiC1 (i = 0 or 1);
The UiC0 register (i=0 or 1) revised.
275 Table 15.5 Registers Used and Settings for UART Mode revised.
Table 15.6 I/O Pin Functions in UART Mode revised.
276 Figure 15.10 Transmit Timing in UART Mode revised.
277 Figure 15.11 Receive Timing Example in UART Mode revised.
279 15.3 Notes on Serial Interface;
“
15.3 Precautions on Serial Interface
” → “
15.3 Notes on Serial Interface
”
revised.
280 16. Clock Synchronous Serial Interface, on the 3rd line;
“
(SSU)
” added.
281 16.2 Clock Synchronous Serial I/O with Chip Select (SSU);
“
(SSU)
” added.
Table 16.2 Clock Synchronous Serial I/O with Chip Select Specifications;
NOTE2 deleted.
285 Figure 16.4 SSMR Register revised.
288 Figure 16.7 SSMR2 Register revised.
289 Figure 16.8 Registers SSTDR and SSRDR;
NOTE in the SSTDR register revised.
290 16.2.1 Transfer Clock;
“
φ
” → “
f1
” revised.
296 16.2.5.2 Data Transmission;
“16.2.5.2
Data Transmit
” → “
16.2.5.2 Data Transmission
” revised.
16.2.5.2 Data Transmission, on the 4th line from the bottom;
“
When setting the ~ transmit is enabled.
” deleted.
297 Figure 16.14 Sample Flowchart of Data Transmission (Clock Synchronous
Communication Mode);
NOTE revised.
298 16.2.5.3 Data Reception;
“16.2.5.3
Data Receive
” → “
16.2.5.3 Data Reception
” revised.
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