Digital Standard 3GPP W-CDMA (FDD) SMIQ
1125.5555.03 E-92.186
(TRIGGER...) TRIGGER OUT 1/2
For selecting signals for outputs TRIGOUT 1 and
TRIGOUT 2 in the PARDATA connector.
The times only apply if the internal clock generation
frequency was not modified with the CHIP RATE
VARIATION parameter.
SLOT 0.667 ms slot clock
IEC/IEEE-bus command:
:SOUR:W3GP:TRIG:OUTP1 SLOT
RADIO FRAME 10 ms frame clock
IEC/IEEE-bus command:
:SOUR:W3GP:TRIG:OUTP1 RFR
CHIP SEQUENCE Marker signal for identifying the
PERIOD periodic repetition of the gener-
ated chip sequence
IEC/IEEE-bus command:
:SOUR:W3GP:TRIG:OUTP1 CSP
ENHANCED Marker signal for marking the
CHIP SEQUENCE periodic repetition of generated
PERIOD enhanced chip sequence (only
displayed with option SMIQB48
installed).
IEC/IEEE-bus command:
:SOUR:W3GP:TRIG:OUTP1 ECSP
P-CCPCH Marker signal for identifying
/BCH SFN the restart of the system
RESTART frame number (SFN Restart)
after 4096 frames (available only
when option SMIQB48 is installed
and a P-CCPCH/BCH is
generated).
IEC/IEEE-bus command:
:SOUR:W3GP:TRIG:OUTP1 SFNR
TRIGGER OUT 1/2 POL
Selects the polarity of signals at the TRIGOUT 1 and
TRIGOUT 2 outputs in the PARDATA connector.
IEC/IEEE-bus :SOUR:W3GP:OUTP2:POL POS
TRIGGER OUT 1/2
DELAY
Setting of the number of chips by which the selected
trigger output signal is delayed.
IEC/IEEE-bus :SOUR:W3GP:OUTP2:DEL 0
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