STR-ZA1000ES/ZA2000ES/ZA3000ES
STR-ZA1000ES/ZA2000ES/ZA3000ES
4444
6-6. BLOCK DIAGRAM - HDMI OUTPUT Section -
102(PROG_VURX)
101(PROG_VUTX)
UART_VU/SEL2
UART_SEL2/VU
6RG_TX_INT_0
2RG_TX_RESET_0
>014B
UART_SEL2/VU, UART_VU/SEL2
B18 RX_0P
A18 RX_0N
B19 RX_1P
A19 RX_1N
B20 RX_2P
A20 RX_2N
B17 R X _ C P
A17 R X _ C N
C16 R X _ H P D
B12 X T A L P
AA15
DDR_CK
B8
A8
MISO1
MOSI1
ADV8003_SPSF_DIN
ADV8003_SPSF_DOUT
135
134
RG_TX_SDA
RG_TX_SCK
3
4
C8SCK1
D8
C10
/CS1
INT0
D10INT1
D11
C11
INT2
PDN
A11/RESET
ADV8003_SPSF_SCK
133
ADV8003_SPI_CS
128
ADV8003_INT0
132
ADV8003_INT1
131
ADV8003_INT2
130
ADV8003_P_DOWN
139
ADV8003_RESET
136
K22
K23
J22
J23
H22
H23
L22
L23
J20
K20
L20
TX1_0+
TX1_0–
TX1_1+
TX1_1–
TX1_2+
TX1_2–
TX1_C+
TX1_C–
DDC1_SDA
DDC1_SCL
HPD_TX1
7DATA0+
9DATA0–
4DATA1+
6DATA1–
1DATA2+
3DATA2–
10 CLOCK+
12 CLOCK–
16 SDA (5V)
15 SCL (5V)
19 HOT PLUG DET
CN5012
HDMI [4K]
HDCP 2.2
ARC
OUT A
VIDEO SYSTEM CONTROLLER
IC3003 (4/5)
CK
DDR_DQ [0] –
DDR_DQ [15]
DQ0 – DQ15
A0 – A12
DDR_A [0] –
DDR_A [12]
1616
13
Y15 DDR_/CK
AB15
DDR_CKE
AB13
DDR_BA [0]
AC13
DDR_BA [1]
AC14
DDR_BA [2]
AA13
DDR_/CS
AB14
DDR_/RAS
Y13 DDR_/CAS
AC15
DDR_/WE
AA19
DDR_DM [1]
AB17
DDR_DQS [1]
AC18
DDR_/DQS [1]
AA20
DDR_DM [0]
AB22
DDR_DQS [0]
AC22
DDR_/DQS [0]
AB6 DDR_DM [3]
Y7 DDR_DQS [3]
AA7 DDR_/DQS [3]
AB4 DDR_DM [2]
Y3 DDR_DQS [2]
AA4 DDR_/DQS [2]
13
J8
/CK
K8
CKE
K2
BA0
L2
BA1
L3
BA2
L1
/CS
L8
/RAS
K7
/CAS
L7
/WE
K3
UDM
B3
UDQS
B7
/UDQS
A8
LDM
F3
LDQS
F7
/LDQS
E8
SD-RAM
IC3203
SD-RAM
IC3200
CK
DDR_DQ [16] –
DDR_DQ [31]
DQ0 – DQ15
A0 – A12
16
13
J8
/CK
K8
CKE
K2
BA0
L2
BA1
L3
BA2
L1
/CS
L8
/RAS
K7
/CAS
L7
/WE
K3
UDM
B3
UDQS
B7
/UDQS
A8
LDM
F3
LDQS
F7
/LDQS
E8
VIDEO PROCESSOR
IC3202
HDMI TRANSCEIVER
IC3502 (2/2)
SERIAL FLASH
IC5009
64SPI_MISO
63SPI_MOSI
60SPI_CLK
61SPI_CS0
DO (IO1)
2
DI (IO0)
5
CLK
6
CS
1
SERIAL FLASH
IC3206
B10MISO2
B9MOSI2
A9SCK2
A10/CS2
SO
2
SI
5
SCK
6
/CS
1
12 RX0P
11 RX0N
14 RX1P
13 RX1N
16 RX2P
15 RX2N
8RXCP
7RXCN
76 DADA
75 DSCL
4RX_HPD
69 CSDA
68 CSCL
20 INT
34 RESETN
43
42
45
44
47
46
41
40
67
66
38
TX0P
TX0N
TX1P
TX1N
TX2P
TX2N
TXCP
TXCN
TDSDA
TDSCL
TX_CBUS_HPD
14 RESERSE (NC)
13 CEC
D7SDA
C7SCL
HDMI TRANSMITTER
IC5010
RY001
RELAY
DRIVE
Q001
CEC DATA
SWITCH
Q8005 – 8008
CEC_RX
CEC_TX
CEC_PCONT
>013B
CEC_PCONT,
CEC_TX, CEC_RX
I2C_SDA
I2C_SCL
CEC
>012B
I2C_SDA, I2C_SCL, CEC
>002B
ARC_SPDIF
7DATA0+
9DATA0–
4DATA1+
6DATA1–
1DATA2+
3DATA2–
10 CLOCK+
12 CLOCK–
16 SDA (5V)
15 SCL (5V)
19 HOT PLUG DET
CN5013
HDMI [4K]
HDCP 2.2
(ZONE 2)
OUT B
HDMI [4K]
(ZONE 2)
OUT B
155
154
157
156
159
158
153
152
109
11 0
105
T0X0+
T0X0–
T0X1+
T0X1–
T0X2+
T0X2–
T0XC+
T0XC–
TXDSDA1
TXDSCL1
TX_HPD0
11 4XTALIN
145
144
147
146
149
148
143
142
108
T1X0+
T1X0–
T1X1+
T1X1–
T1X2+
T1X2–
T1XC+
T1XC–
TX_HPD1
T1X0–
T1X1+
T1X0+
OUT1_SDA
T1X1–
T1X2–
T1XC–
T1XC+
T1X2+
OUT1_HPD
OUT1_SDL
T1X0–
T1X1+
T1X0+
OUT1_SDA
T1X1–
T1X2–
T1XC–
T1XC+
T1X2+
OUT1_HPD
OUT1_SDL
B4 AUD_IN [0]
A4 AUD_IN [1]
A5 AUD_IN [2]
B5 AUD_IN [3]
C4 AUD_IN [4]
A6 AUD_IN [5]
D6 MCLK
C6 SCLK
C5 DSD_CLK
124
126
127
128
130
122
121
125
SDO_0/DL0
SDO_1/DR1/GPIO6
SDO_2/DL1/GPIO7
SDO_3/DR2/GPIO8
SPDIF0_OUT/DL2
SCK0/DDCK
WS0_OUT/DR0
MCLK
136
SD1_IN/SD1_OUT/S
PDIF1_IN/
SPDIF1_OUT
SD1
SD2
SD0
SD3
BCK
SPDIF1_OUT
LRCK
SPDIF
MCK
>001B
SD0 – SD3, SPDIF, BCK,
LRCK, MCK, SPDIF1_OUT
CLOCK
BUFFER
IC3501
X3500
27MHz
UART_VU/MU, UART_MU/VU, MD0_MU/VU,
ENDFLAG_VU/MU, RESET_MU/VU
63UART TX (VU2MU)
62UART RX (MU2VU)
49INTIX
RESET_MU/VU
UART_MU/VU
UART_VU/MU
69MD0
MD0_MU/VU
64ENDFLAG_VU/MU
ENDFLAG_VU/MU
>015B
–1
7RG_TX_INT_1
5RG_TX_RESET_1
HDMI TRANSMITTER
IC5011
12 RX0P
11 RX0N
14 RX1P
13 RX1N
16 RX2P
15 RX2N
8RXCP
7RXCN
76 DSDA
75 DSCL
4RX_HPD
TX0P 43
TX0N
42
TX1P
45
TX1N
44
TX2P
47
TX2N
46
TXCN
40
TXCP
41
20 34
INT
RESETN
SERIAL FLASH
IC5013
64SPI_MISO
63SPI_MOSI
60SPI_CLK
61SPI_CS0
DO (IO1)
2
DI (IO0)
5
CLK
6
CS
1
(ZA1000ES/ZA2000ES)
(ZA1000ES/ZA2000ES)
(ZA3000ES)
67
66
38
TDSDA
TDSCL
TX_CBUS_HPD
(ZA1000ES/ZA2000ES)
(ZA3000ES)
RESET SWITCH
Q3003
RESET SWITCH
Q3004
X171
X0
70
X3000
4MHz
69 CSDA
68 CSCL
: AUDIO
: VIDEO
SIGNAL PATH
(Page 47)
(Page 39)
(Page 39)
(Page 43)
(Page 47)
(Page 47)
Ver. 1.1
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