TB7100 Installation and Operation Manual Functional Description 31
© Tait Electronics Limited December 2005
Bias Ramp-up
The steady-state final-stage bias level is supplied by an 8-bit DAC
programmed prior to ramp-up but held to zero by a switch on the DAC
output under the control of a
TX INHIBIT signal. Bias ramp-up begins upon
release by the
TX INHIBIT signal with the ramping shape being determined by
a low-pass filter. Owing to power leakage through the PA chain, ramping
the bias takes the PA output power from less than –20dBm for the
50W/40W version or –10dBm for the 25W version to approximately
25dB below steady-state power.
Power Ramp-up The power ramp signal is supplied by a 13-bit DAC that is controlled by
custom logic. The ramp is generated using a look-up table in custom logic
memory that is played back at the correct rate to the DAC to produce the
desired waveform. The ramp-up and ramp-down waveforms are produced
by playing back the look-up table in forward and reverse order respectively.
For a given power level the look-up table values are scaled by a steady-state
power constant so that the ramp waveform shape remains the same for all
power levels.
Figure 3.4 Typical ramping waveforms
Power
ramp
High power
powerLow
Power
Time
Bias
ramp
Bias
ramp
Power
ramp
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