AM3359, AM3358, AM3357, AM3356, AM3354, AM3352
SPRS717H –OCTOBER 2011–REVISED MAY 2015
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External Memory Interfaces/General Purpose Memory Controller Signals Description (continued)
TYPE
SIGNAL NAME [1] DESCRIPTION [2] ZCE BALL [4] ZCZ BALL [4]
[3]
gpmc_a27 GPMC Address O NA V17
gpmc_a3 GPMC Address O U17, V2 R4, T13, T14
gpmc_a4 GPMC Address O W2 R14, T1
gpmc_a5 GPMC Address O W3 T2, V15
gpmc_a6 GPMC Address O V3 T3, U15
gpmc_a7 GPMC Address O U3 T15, T4
gpmc_a8 GPMC Address O U7 U5, V16
gpmc_a9 GPMC Address O T7 R5, U16
gpmc_ad0 GPMC Address and Data I/O W10 U7
gpmc_ad1 GPMC Address and Data I/O V9 V7
gpmc_ad10 GPMC Address and Data I/O T12 T11
gpmc_ad11 GPMC Address and Data I/O U12 U12
gpmc_ad12 GPMC Address and Data I/O U13 T12
gpmc_ad13 GPMC Address and Data I/O T13 R12
gpmc_ad14 GPMC Address and Data I/O W17 V13
gpmc_ad15 GPMC Address and Data I/O V17 U13
gpmc_ad2 GPMC Address and Data I/O V12 R8
gpmc_ad3 GPMC Address and Data I/O W13 T8
gpmc_ad4 GPMC Address and Data I/O V13 U8
gpmc_ad5 GPMC Address and Data I/O W14 V8
gpmc_ad6 GPMC Address and Data I/O U14 R9
gpmc_ad7 GPMC Address and Data I/O W15 T9
gpmc_ad8 GPMC Address and Data I/O V15 U10
gpmc_ad9 GPMC Address and Data I/O W16 T10
gpmc_advn_ale GPMC Address Valid / Address Latch Enable O V10 R7
gpmc_be0n_cle GPMC Byte Enable 0 / Command Latch Enable O V8 T6
gpmc_be1n GPMC Byte Enable 1 O U15, V18 U18, V9
gpmc_clk GPMC Clock I/O V14, V16 U9, V12
gpmc_csn0 GPMC Chip Select O W8 V6
gpmc_csn1 GPMC Chip Select O V14 U9
gpmc_csn2 GPMC Chip Select O U15 V9
gpmc_csn3 GPMC Chip Select O U17 T13
gpmc_csn4 GPMC Chip Select O R15 T17
gpmc_csn5 GPMC Chip Select O W18 U17
gpmc_csn6 GPMC Chip Select O V18 U18
gpmc_dir GPMC Data Direction O V18 U18
gpmc_oen_ren GPMC Output / Read Enable O W9 T7
gpmc_wait0 GPMC Wait 0 I R15 T17
gpmc_wait1 GPMC Wait 1 I V16 V12
gpmc_wen GPMC Write Enable O U8 U6
gpmc_wpn GPMC Write Protect O W18 U17
56 Terminal Configuration and Functions Copyright © 2011–2015, Texas Instruments Incorporated
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