162
/* User initialization code */
/* USER CODE END (section: GPIO_graceInit_prologue) */
/* Port 1 Output Register */
P1OUT = 0;
/* Port 1 Port Select Register */
P1SEL = BIT7;
/* Port 1 Direction Register */
P1DIR = BIT0 | BIT6 | BIT7;
/* Port 1 Interrupt Edge Select Register */
P1IES = 0;
/* Port 1 Interrupt Flag Register */
P1IFG = 0;
/* Port 2 Output Register */
P2OUT = 0;
/* Port 2 Port Select Register */
P2SEL &= ~(BIT6 | BIT7);
/* Port 2 Direction Register */
P2DIR = 0;
/* Port 2 Interrupt Edge Select Register */
P2IES = 0;
/* Port 2 Interrupt Flag Register */
P2IFG = 0;
/* Port 3 Output Register */
P3OUT = 0;
/* Port 3 Direction Register */
P3DIR = 0;
/* USER CODE START (section: GPIO_graceInit_epilogue) */
/* User code */
/* USER CODE END (section: GPIO_graceInit_epilogue) */
}
void Comparator_Aplus_graceInit(void)
{
/* USER CODE START (section: Comparator_Aplus_graceInit_prologue) */
/* User initialization code */
/* USER CODE END (section: Comparator_Aplus_graceInit_prologue) */
/* CACTL1 Register */
CACTL1 = CAREF_2 | CAON | CAIES | CAIE;
/* CACTL2 Register */
CACTL2 = P2CA3 | P2CA1;
/* CAPD, Register */
CAPD = CAPD5;