Texas Instruments MSP430

221
/* USER CODE START (section: USI_graceInit_prologue) */
/* User initialization code */
/* USER CODE END (section: USI_graceInit_prologue) */
/* Disable USI */
USICTL0 |= USISWRST;
/*
* USI Control Register 0
*
* ~USIPE7 -- USI function disabled
* USIPE6 -- USI function enabled
* USIPE5 -- USI function enabled
* ~USILSB -- MSB first
* USIMST -- Master mode
* ~USIGE -- Output latch enable depends on shift clock
* USIOE -- Output enabled
* USISWRST -- USI logic held in reset state
*
* Note: ~<BIT> indicates that <BIT> has value zero
*/
USICTL0 = USIPE6 | USIPE5 | USIMST | USIOE | USISWRST;
/*
* USI Clock Control Register
*
* USIDIV_3 -- Divide by 8
* USISSEL_2 -- SMCLK
* USICKPL -- Inactive state is high
* ~USISWCLK -- Input clock is low
*
* Note: ~USISWCLK indicates that USISWCLK has value zero
*/
USICKCTL = USIDIV_3 | USISSEL_2 | USICKPL;
/* Enable USI */
USICTL0 &= ~USISWRST;
/* USER CODE START (section: USI_graceInit_epilogue) */
/* User code */
/* USER CODE END (section: USI_graceInit_epilogue) */
}
void System_graceInit(void)
{
/* USER CODE START (section: System_graceInit_prologue) */
/* User initialization code */
/* USER CODE END (section: System_graceInit_prologue) */
/* Clear oscillator fault flag with software delay */
do
{
// Clear OSC fault flag
IFG1 &= ~OFIFG;
// 50us delay
__delay_cycles(50);
} while (IFG1 & OFIFG);