255
void USCI_B0_graceInit(void)
{
/* USER CODE START (section: USCI_B0_graceInit_prologue) */
/* User initialization code */
/* USER CODE END (section: USCI_B0_graceInit_prologue) */
/* Disable USCI */
UCB0CTL1 |= UCSWRST;
/*
* Control Register 0
*
* UCCKPH -- Data is captured on the first UCLK edge and changed on the
following edge
* ~UCCKPL -- Inactive state is low
* UCMSB -- MSB first
* ~UC7BIT -- 8-bit
* UCMST -- Master mode
* UCMODE_1 -- 4-Pin SPI with UCxSTE active high: slave enabled when UCxSTE =
1
* UCSYNC -- Synchronous Mode
*
* Note: ~<BIT> indicates that <BIT> has value zero
*/
UCB0CTL0 = UCCKPH | UCMSB | UCMST | UCMODE_1 | UCSYNC;
/*
* Control Register 1
*
* UCSSEL_2 -- SMCLK
* UCSWRST -- Enabled. USCI logic held in reset state
*/
UCB0CTL1 = UCSSEL_2 | UCSWRST;
/* Bit Rate Control Register 0 */
UCB0BR0 = 8;
/* Enable USCI */
UCB0CTL1 &= ~UCSWRST;
/* USER CODE START (section: USCI_B0_graceInit_epilogue) */
/* User code */
/* USER CODE END (section: USCI_B0_graceInit_epilogue) */
}
void System_graceInit(void)
{
/* USER CODE START (section: System_graceInit_prologue) */
/* User initialization code */
/* USER CODE END (section: System_graceInit_prologue) */
/*
* SR, Status Register
*
* ~SCG1 -- Disable System clock generator 1
* ~SCG0 -- Disable System clock generator 0
* ~OSCOFF -- Oscillator On
* ~CPUOFF -- CPU On