371
/* USER CODE START (section: BCSplus_graceInit_epilogue) */
/* User code */
/* USER CODE END (section: BCSplus_graceInit_epilogue) */
}
void USCI_A0_graceInit(void)
{
/* USER CODE START (section: USCI_A0_graceInit_prologue) */
/* User initialization code */
/* USER CODE END (section: USCI_A0_graceInit_prologue) */
/* Disable USCI */
UCA0CTL1 |= UCSWRST;
/*
* Control Register 0
*
* ~UCPEN -- Parity Disabled
* UCPAR -- Even parity
* ~UCMSB -- LSB first
* ~UC7BIT -- 8-bit
* ~UCSPB -- One stop bit
* UCMODE_0 -- UART Mode
* ~UCSYNC -- Asynchronous mode
*
* Note: ~<BIT> indicates that <BIT> has value zero
*/
UCA0CTL0 = UCPAR | UCMODE_0;
/*
* Control Register 1
*
* UCSSEL_2 -- SMCLK
* ~UCRXEIE -- Erroneous characters rejected and UCAxRXIFG is not set
* ~UCBRKIE -- Received break characters do not set UCAxRXIFG
* ~UCDORM -- Not dormant. All received characters will set UCAxRXIFG
* ~UCTXADDR -- Next frame transmitted is data
* ~UCTXBRK -- Next frame transmitted is not a break
* UCSWRST -- Enabled. USCI logic held in reset state
*
* Note: ~<BIT> indicates that <BIT> has value zero
*/
UCA0CTL1 = UCSSEL_2 | UCSWRST;
/*
* Modulation Control Register
*
* UCBRF_0 -- First stage 0
* UCBRS_1 -- Second stage 1
* ~UCOS16 -- Disabled
*
* Note: ~UCOS16 indicates that UCOS16 has value zero
*/
UCA0MCTL = UCBRF_0 | UCBRS_1;
/* Baud rate control register 0 */
UCA0BR0 = 104;
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