53
P1OUT = 0;
/* Port 1 Direction Register */
P1DIR = BIT0 | BIT6;
/* Port 1 Interrupt Edge Select Register */
P1IES = BIT3;
/* Port 1 Interrupt Flag Register */
P1IFG = 0;
/* Port 1 Interrupt Enable Register */
P1IE = BIT3;
/* Port 2 Output Register */
P2OUT = 0;
/* Port 2 Port Select Register */
P2SEL &= ~(BIT6 | BIT7);
/* Port 2 Direction Register */
P2DIR = 0;
/* Port 2 Interrupt Edge Select Register */
P2IES = 0;
/* Port 2 Interrupt Flag Register */
P2IFG = 0;
/* USER CODE START (section: GPIO_graceInit_epilogue) */
/* User code */
/* USER CODE END (section: GPIO_graceInit_epilogue) */
}
void System_graceInit(void)
{
/* USER CODE START (section: System_graceInit_prologue) */
/* User initialization code */
/* USER CODE END (section: System_graceInit_prologue) */
/* Clear oscillator fault flag with software delay */
do
{
// Clear OSC fault flag
IFG1 &= ~OFIFG;
// 50us delay
__delay_cycles(50);
} while (IFG1 & OFIFG);
/*
* SR, Status Register
*
* ~SCG1 -- Disable System clock generator 1
* ~SCG0 -- Disable System clock generator 0
* ~OSCOFF -- Oscillator On
* ~CPUOFF -- CPU On
* GIE -- General interrupt enable